1 outline
The LonWorks field bus (the i.e. LON main line) is the partial operation network which American Echelon Corporation promotes, provided very strongly for the collection and distribution type supervisory system has realized the method, becomes one which of field bus technologies is popular now. In present’s observation system, connects in the field bus network each node, namely the sensor, the transmitting instrument, the actuator and so on no longer are the single function traditional measuring appliances, but has function and so on data acquisition, transformation, control, computation, warning, diagnosis and digital communication intellectualized equipment (intelligent node) connects in the network each kind of intelligence field apparatus sharing main line channel, carries on the data and the exchange of information, the intercoordination work composes a complete field bus control system. The LON bussing technique uses open style communication protocol LonTalk, exchanged the control state information for the equipment between to establish an general standard and, has realized timeliness and the connection under the hardware chip’s support direct-viewing, the succinct field bus’s application request. All nodes include one in the LON bussing technique to use to realize function and so on communication management, input, output and control neuron chips (Neuron Chip)– The LON bussing technique’s core, it is not only the LON main line’s correspondence processor, is also the data acquisition and the control general processor, in the LON bussing technique all network operation in fact is completes through it. Therefore in the network the node design is realizes a LON bussing technique key to be.
2 intelligent node development general method
The intelligent node is in the directed net distributes in the scene level basic intelligent unit, mainly uses in accepting and processing from sensor’s data-, the execution corresponds and controls the duty as well as the control carries out the operation and so on. In the intelligent node’s core technologies is the LONTALK agreement and the neuron chip. The intelligent node’s development divides into two kinds: One kind is completes all work using the neuron chip (including correspondence and user application procedure), in the node no longer contains other processors. This kind of intelligent node becomes based on the neuron chip node. Another kind only completes the correspondence work using the neuron chip, but user’s application procedure by other processors (for example microprocessor, micro controller or PC machine completes) this kind of intelligent node to become based on main engine’s node.
(1) take the Neuron chip as core control node
Figure 1 is take the Neuron chip as the core control node structure diagram.
The neuron chip is a group of complex VLSI component, unifies the technology through the unique hardware firmware, causes a Neuron chip to contain a scene node nearly the majority of functions, if adds on the transceiver to be possible to constitute a typical scene control node.
Because this design method the Neuron chip is 8 main lines, at present supports the highest basic frequency is only 10MHz, therefore it can complete the function is also very limited, like has the PID algorithm single return route multi-loop control regarding some complex controls appears lacks the ability to do what one would like. And its piece carries the operating system to inspect the mechanism based on one kind, not too suitably in timely very strong control node.
Figure 1 take the Neuron chip as core control node structure
Figure 2 uses the MIP structure the control node structure
(2) uses the MIP structure the control node
Figure 2 is Host the Base structure node diagram. In view of the fact that method (1) the shortcoming, uses the MIP structure solves this question good means that cooperates the processor the Neuron chip as the correspondence, with high-quality main engine (superior supervisor) the resources complete the complex observation function.
Regarding this method, because the high-quality main engine (superior supervisor) and various intelligent node, belongs many to a correspondence, when the node increases, easy to cause network blocking, once and has the network congestion, in the network data transmission efficiency will reduce obviously.
In addition, in the existing mostly LON network’s intelligent node application, the data acquisition system usually uses the monolithic integrated circuit or DSP (digital signal processor) takes CPU, controls ADC (mold/number switch), the memory and other peripheral circuit’s work. But monolithic integrated circuit’s clock rate is low, adapts the high speed data gathering system’s request with difficulty, but DSP, although may realize the high speed data acquisition, but its speed enhances at the same time also enhanced system’s cost. FPGA (the scene programmable gate array) has the superiority which the monolithic integrated circuit and DSP are unable to compare: The clock rate is high, the internal latency is small; The complete control logic completes by the hardware, the speed is quick, the efficiency is high; The composition form is flexible, may integrate the periphery control, the decoding and the interface circuit.
3 high speed intelligent node design
3.1 high speed intelligent node hardware system structural design
This high speed intelligent node is designs based on the FPGA construction. FPGA is overall system’s control center and the data exchange bridge, moreover can realize to the first floor signal pretreats fast, in many signal processing system, the data quantity which the first floor signal pretreatment algorithm needs to process is very big, is very high to the processing speed request, but the algorithm structure is relatively quite simple, is suitable for to carry on the hardware programming with FPGA to realize.
System’s functional block diagram as shown in Figure 3.
Figure 3 general high speed intelligent node gross structure diagram
The entire high speed data gathering processing system’s main hardware constitution is:
1) ACEX1K series EP1K30TC144-3: The main processor, is overall system’s control center and the data processing center, the characteristic is the electric circuit connects the I/O mouth, the speed is quick;
2) AD9288: Realizes 4 groups 8 sampling, the highest sampling frequency is 100 MSPS, suits the application and the high speed signal measurement instrument; ;
3) Neuron chip: The correspondence cooperates the processor, is responsible to correspond the function
4) pair of mouth RAM: The main processor and the correspondence cooperate processor’s connection, realizes the data exchange;
5) transceiver FTT-10A: Data transfer to the LON main line.
Issues the gathering instruction or under timer’s function in the control bench, the analog input enters FPGA after the AD sampling, after passing through in FPGA the signal processing module and algorithm processing, stores RAM, after Neuron chip read-out to the LON network.
3.2 high speed intelligent node software design
The software design includes: Data acquisition and control.
1) data acquisition software design
After the data acquisition the superior machine issues the gathering data command, delivers the corresponding node through the network variable, then controls the exterior sensor execution corresponding data acquisition instruction, and will gather the data delivers the neuron chip after a/D transformation, after the network variable transmission, dynamic data connection transmits again after LNS the DDE for monitors the software, and carries on the presente in figures and diagrams demonstration to give the operator. This flow may circulate unceasingly carries on, until satisfies all conditions. This part of overall flow as shown in Figure 4.
Figure 4 gathering procedure software flow chart Figure 5 control procedure software flow chart
Data acquisition partial core software: This part of major functions are the simulated signal which gathers after the level switch, the filter and the multiway switches divides into 8 groups signals, carries on a/D transformation to turn the digital quantity again, after undergoing processing processing, delivers to the network database, automatic rewriting network variable value.
2) control software design
The control software is mainly is responsible for the first floor equipment’s control. When the control center in monitors the software to after-crop the control command, transmits after DDE for the LonWorks network, delivers corresponding through the network variable the node, in transforms after D/A, after first floor equipment receive, starts the data acquisition, then carries on examines whether to have the next control command. This flow is also may circulate unceasingly until satisfies all conditions. This part of overall flow as shown in Figure 5.
3.3 experimental results
Inputs a sine wave, the cycle is 1s, obtains like Figure 6 to show the result:
Figure 6 experimental result
4 concluding remark
This designed successfully realizes has taken the LON network intelligence node using the FPGA chip the main processor, and used pair of mouth RAM to realize between the main processor and the NEURON chip data transfer. This system suits the majority data acquisition situation, can serve general and the high speed purpose.
Uses FPGA to carry on the design to be possible to reduce the development production cycle, moreover the scene flexibility is good, not only it has included MCU this characteristic, moreover may touch the silicon chip electric circuit’s physical boundary, and has at the same time the string, the multi-tasking way, high speed, redundant reliability as well as wide aperture serviceable and so on many aspect characteristics. Therefore, uses based on the FPGA LON network high speed intelligent node design has certain practical significance and the value.
