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Multi-purpose digital clock which compiles with verilog_Verilog, digital clock
Friday, December 18th, 2009 at 23:50 | No commentsCategories: EDA/PLDTags: digital clock, VerilogShort Content: /* signal definition:clk: The standard clock signal, in this example, its frequency is 4Hz;clk_1k: Has the alarum sound, to report time the sound clock signal, in this example its frequency is 1024Hz;mode: Functional control signal; For 0: Time function;For 1: Alarm clock function;For 2: Manual timing function;turn: Meets the pressed key, when manual timing function, the choice is adjusts the hour, minute;If the long time holds down this, but may also cause the second signal reset, uses in the ... -
In Verilog mold train (module) concept_Verilog, modules
Friday, December 18th, 2009 at 22:05 | No commentsCategories: EDA/PLDShort Content: Mold train (module) concept -------------------------------------------------------------------------------- In the Verilog elemental area is the mold train (module).The mold train represents some may use the logic entity which the hardware practices. For example, a mold train may be a logical floodgate, a 32 element counter, a memory subsystem, machine calculated that machine the system perhaps use the network connected many computers.In the mold train and the outside coupling end (port) may be an element or several elements. The coupling end may ... -
Bilateral circuit design experience_inout, bi-directional signal
Friday, December 18th, 2009 at 21:10 | No commentsCategories: EDA/PLDTags: bi-directional signal, inoutShort Content: In the project application, the bilateral circuit is the question which the designer can not but face. In the practical application, the data bus often is bidirectional. How processes the data bus is correctly carries on the sequential logic circuit design the foundation. In the programming process, the key technologies lies in: The entity part must carry on the declaration to the port attribute, the port attribute must be the inout type, is constructing the body to need to ... -
Odd and even calibrator_VHDL, parity device
Friday, December 18th, 2009 at 18:31 | No commentsCategories: EDA/PLDTags: parity device, VHDLShort Content: The procedure is very simple, but may expand to the small detail library IEEE;use IEEE.std_logic_1164.all; entity parity is port ( a: in STD_LOGIC_VECTOR (8 downto 0); b: out STD_LOGIC );end parity; architecture parity_arch of parity is begin process(a) variable even:std_logic; begin even:='0'; for i in a'range loop if a(i)='1' then even:=not even; end if; end loop; b -
Verilog the study writes down_Verilog, assign
Friday, December 18th, 2009 at 16:46 | No commentsCategories: EDA/PLDShort Content: Generally thoughtVerilog HDL in system-level abstract aspect compared to VHDL slightly bad somewhat, but in gate step switch electric circuit description aspect compared to VHDL striving to excel many Has written the first verilog procedure, is an accumulator content is as followsmodule adder(count, sum, a, b, cin);input[2:0] a, b;input cin;output count;output [2:0] sum;assign{count, sum}=a b cin;endmodule Started to translate presented several mistakes, afterward discovered that the entity wanted consistently for in the entity naming and the procedure and the ... -
Based on VHDL asynchronous serial communication circuit design_VHDL, asynchronous communication
Friday, December 18th, 2009 at 15:01 | No commentsCategories: EDA/PLDTags: asynchronous communication, VHDLShort Content: 1 introduction Along with electronic technology's development, scene programmable gate array FPGA and the complex programmable logical component CPLD appearance, causes the electronic system's designer use and the component corresponding electron CAD software, may design own specific IC ASIC component in the laboratory. This kind of programmable ASIC not only enables the design the product to achieve the miniaturization, the integration and the redundant reliability, moreover the component has the user programmable characteristic, reduced the design cycle greatly, reduced ... -
Based on FPGA autonomous SPWM profile generator design_FPGA, SPWM
Friday, December 18th, 2009 at 14:06 | No commentsCategories: EDA/PLDShort Content: Abstract: This article in view of static compensator (STATCOM) to window signal's request, has designed one kind based on the FPGA sine pulse-duration modulation (SPWM) the profile generator. Through the sine modulating wave and the triangle carrier's comparison, has produced six group PWM signal impulse. The sine modulating wave's production uses the table look-up law, but only stores 1/4 cycle's sine wave data in ROM which the FPGA interior hardware constructs, reduced system's hardware expenses, the simulation result has ... -
In the VHDL design
Friday, December 18th, 2009 at 12:22 | No commentsCategories: EDA/PLDTags: circuit simplification, VHDLShort Content: Abstract: From the description method, the design rule, the logical function analyzed in the VHDL design easy to cause the electric circuit complication reason, and proposed the corresponding solution. In recent years, along with the integrated circuit technology's development, carried on the chip or the system design with the traditional method has not been able to satisfy the request, urgent needs to raise the rated capacity. Under such technical background, can reduce the design difficulty the VHDL ... -
Low voltage PLD / FPGA power supply design_FPGA, power supply
Friday, December 18th, 2009 at 11:27 | No commentsCategories: EDA/PLDTags: FPGA, Power SupplyShort Content: As a result of the semiconductor fabrication technology's reason, the low voltage component's cost is lower than the traditional 5V component, the performance is more superior, in addition the most component's I/O feet may compatible 5v/3.3v the TTL level, be possible to use directly in the original system, therefore each big semiconductor company low voltage integrated circuits and so on 3.3v,2.5v takes the promotion key, if the high-end DSP, PLD/FPGA product has widely used 3.3v,2.5v even the 1.8v,1.5v power ... -
Verilog code compilation standard_Verilog, code specifications
Friday, December 18th, 2009 at 09:42 | No commentsCategories: EDA/PLDTags: code specifications, VerilogShort Content: One. Emphasizes the Verilog code compilation style the necessity. Stressed that the Verilog code compilation standard, is the topic which frequently not too receives welcome, but is actually has the necessity.Each code editors have own compilation custom, moreover likes deferring to own custom to compile the code. Compiles the style close code with, reads easy to accept and to understand. On the contrary and compile the style difference big code, reads and accepts difficult somewhat. Once some programmed master ...
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