Abstract: Motolora Corporation’s MCl45163P is the CMOS large scale integration phase-lock frequency synthesizer, the interior includes refers to the frequency divider, two phase comparators and 4 BCD/N frequency dividers, coordinates the ring circuit filter and the pressure controls the oscillator to be possible to obtain one completely, the practical phase-lock frequency synthesizer. In the article introduced the MCl45163P key property, and unified the practical application to introduce in detail controlled the phase-lock frequency synthesis electric circuit which by MCl45163P and the TTL pressure oscillator 74LS628 was composed, gave the actual metrical data.
Key word: Phase-locked loop; Frequency synthesizer; The pressure controls the vibration; Frequency divider
1 outline
Phase-locked loop (PLL) is one kind take eliminates the frequency error as the goal automatic circuit, it uses the phase error signal voltage to eliminate the frequency error. Inserts the frequency divider in the basic PLL feedback path, may constitute the phase-lock frequency synthesizer, electric circuit composition diagram as shown in Figure 1. When the ring circuit locks, fr=fv, namely f0=Nfr.
Motolora Corporation’s MCl45163P is the CMOS large scale integration phase-lock frequency synthesizer. Its interior including Figure 1 dotted portion. The user only need act according to the practical application choice, the design appropriate ring circuit filter and the pressure controls the oscillator, may compose a complete PLL frequency synthesis electric circuit.
2 MCl45163P introductions
2.1 key properties
Figure 2 is the MCl45163P pin arrangement, Figure 3 is its internal structure diagram, Table 1 is the .MCl45163P pin functional description, Table 2 is its electrical specification.
Table 1 MC145163P pin function
| Pin | Merit Can Tracing Station |
| 1 | fin: Frequency synthesizer’s programmable counter (÷N frequency division) input end. Obtains fin from VCO after the electric capacity alternating current coupling to 1 foot |
| 2 | Vss: |
| 3 | VDD: Positive electricity source ( 5V) |
| 4 | PDout: The phase comparator A output, usually takes VCO after the ring circuit filter the control signal. Frequency fv>fr or fv leading of phase; Negative pulse; Frequency fv<fr or fv lagging of phase: Pulse; Frequency fv=fr or with phase: High-resistance condition. See also Figure 4 |
| 5th, 6 | RA0, RA1 four kind of combination decision reference frequency divider (R counter) frequency division ratio. RA1, the RA0=00 frequency division compares 512; RA1, the RA0=01 frequency division compares 1024; RA1, the RA0=10 frequency division compares 2048; RA1, the RA0=11 frequency division compares 4096 |
| 7th, 8 | φR, φV: Phase comparator B output. Frequency. Leads fv>fr or fv leading of phase. φV for the low level pulse, φR maintains the high level; Frequency. Leads fv<fr or the fv lagging of phase. φR for the low level pulse, φV maintains the high level; Frequency fv=fr or with phase; φV, φR is the narrow low level pulse. See also Figure 4. |
| 9-24 | BCD input: 9 feet are 10 0 LSB,24 feet are 10 3 MSB. Internal has pulls the resistance, therefore time input opening is the low level. Establishment scope 3~9999 |
| 25 | REFout: Internal datum oscillator or outside reference signal cushion output |
| 26th, 27 | OSCout, OSCin: The crystal oscillator meets the input terminal, the constitution datum oscillator. Matches meets the low-power electric capacity |
| 28 | The LD:PLL ring lock fixed time, the PLL locking detection signal is the high level, the external connection triode actuates the photo tube demonstration |
2.2 MCl45163P phase comparators
May see from Figure 3, phase comparator (PD) is in the PLL important part, in MCl45163P contains two phase comparators (A and B). And phase comparator A is with loses the person signal border distinction phase the electric circuit, this kind of phase comparator only along has an effect to input signal’s rise, has nothing to do with input signal’s dutyfactor, constitutes PLL by this kind of phase comparator, its same ambulacrum and the capture belt with ring circuit filter (LF) have nothing to do with, but is the infinitely great, but on actual will receive the pressure to control the oscillator (VCO) control area the limit. Generally use phase comparator A output PDout controls VCO through the ring circuit filter’s combination the output frequency, so long as fr and the fv phase angle is 0 (rise along), PLL namely is at the fixed condition.
Table 2 MC145163P electrical specifications (when VDD=5V)
| Project and unit | Mark | Minimum value | Typical value | Maximum value |
| Voltage (V) | VDD | 3 | 9 | |
| Quiescent current (A) | IDD | 300 | 1200 | |
| Input low voltage (V) | VIL | 2.5 | 1.5 | |
| Input high voltage (V) | VIH | 3.5 | 2.7 | |
| Input capacity (pF) | CIN | 6 | 10 | |
| Outputs the low level (mV) | VOL | 1 | 50 | |
| Output high voltage (mV) | VOH | 4950 | 4999 |
In the PLL electric circuit another phase comparator B constitutes and produces φR, φV the signal generally by the different ‘OR’ circuit, they state with fr and in fv relational like table l. Figure 4 has given phase comparator A and B output PDout, φR, φV and fr and fv relations.
2.3 refer to the frequency divider and 4 BCD/N counters
Pin RA0 and RAl use for to decide that the MCl45163P materials for internal reference frequency divider’s frequency division compared to, sees table l, chooses the appropriate frequency division ratio. May obtain to the crystal oscillator frequency fs frequency division, then obtains reference frequency fr. Because of frequency synthesizer’s output frequency fo=Nfr, therefore, fr is also outputs the frequency the gap (step frequency).
The MCl45163P interior has 4 BCD/N counters, through establishes 4 BC[] the values, may obtain the N counter (frequency division) accurate value. For example: 4 BCD value establishment is 1000, then in ring circuit N counter (frequency division) the N value is 1000 (pin 24~9 is 0001000000000000). In the MCl45163P BCD connection end has pulls the resistance, therefore the user only need through public carry 5v to be direct the BCD encoder and MCl45163P BC[) connection connection.
3 application examples
3.1 frequency ranges and the frequency step-by-step
Shan Congn frequency division’s establishment scope 3~9999, if the frequency step-by-steps the fr hypothesis is lkHz, then the fc output frequency is 3 kHz~9999kHz, but must receive the VCO output frequency coverage area the limit, selects the VCO component actually according to the author, the survey frequency range can only in 700kHz~9999kHz(fmin~fmax), the ring circuit is at the fixed condition. Moreover, considered the final output profile achieves the dutyfactor is 50% square-waves, therefore may carry on the reshaping, the frequency division in ‘ the VCO output signal add-on 1/2 frequency divider. Therefore here step-by-steps the fr hypothesis the frequency is 2kHz, fo=Nf=1.4MHz-19.998MHz, namely the .fo frequency step-by-steps is 2kHz; Fo’=1/2fo=0.7MHz~9.999MHz which obtains after 1,2 frequency division components, namely the final output signal fo’di frequency step-by-steps is 1kHz.
3.2 BCD addressable port
The author has not used simple revolving or the driving plate type BCD encoder, but designed has used in common keyboard’s 4 BCI) to code the generator and MCl45163P carries on the connection. Presses a key S0-S9 with ten to produce decimal base 0~9 BCI) to code, four press a key S10-S13 to use for to cut the different figure, and with the nixietube real-time demonstrated the current BCD code corresponds decimal digit. Electric circuit diagram as shown in Figure 5, take monolithic integrated circuit AT89C2051 as the core, compiles the 4×4 matrix keyboard’s scanning control disposal procedure, may realize the above pressed key function. Uses this unit electric circuit to obtain the BCD code, the merit lies in is reliable, is convenient, each time only need press down corresponding the position control pressed key (S10-S13) and the corresponding BCD code pressed key (S0-S9). At the same time, may know by the preceding text, the output signal fo frequency step-by-steps is lkHz, therefore the nixietube demonstrated that BCI) codes corresponding the decimal digit is the current PLL frequency synthesizer’s output frequency.
3.3 VCO choices
In TTL series 7415624-74LS629 is six kind of use quite convenient VC() integrated circuit. Mainly contains the VCO quantity by the component, whether the bidirectional output (does eliminate Y output pin, does some belt Z output pin), whether there is enable the end, whether there is the band switching, whether the temperature compensation and so on does make the discrimination. Table 3 are the 74LS5624-74LS629 detailed function discriminations.
Table 3 74LS624-74LS629 detailed function discrimination
| Model | Contains the VCO quantity | The bidirectional output (brings Z output pin) | Enables the end | Band switching pin (RNG) | Temperature compensation end |
| 74LS624 | 1 | Has | Has | Has | Does not have |
| 74LS625 | 2 | Has | Does not have | Does not have | Does not have |
| 74LS626 | 2 | Has | Has | Does not have | Does not have |
| 74LS627 | 2 | Does not have | Does not have | Does not have | Does not have |
| 74LS628 | 1 | Has | Has | Has | Has |
| 74LS629 | 2 | Does not have | Has | Has | Does not have |
Fo=1.4MHz~19.998MHz which as well as front establishes according to various components material, may select 74LS628/74LS624. Figure 6 is its pin arrangement and the function synopsis, pays attention to 74L$628 11, 12 foot labelling is RX, uses in external connection temperature compensation resistance Rext. But 74LS624 1l, 12 feet are hanging foot (NC).
The analysis pressure controls oscillator 74L5628/72LS624 the output frequency to be possible to obtain the following conclusion:
when (1)2 foot band switching control electric potential VRNG, 13 foot electric potential VFC is invariable, 3, 4 foot external connection capacitor Cext is bigger, the output signal frequency is lower, is advantageous in achieves the frequency range lower limit .fmin, but does not favor the frequency range the upper limit. Factory zi; Otherwise, the conclusion is opposite. Must therefore choose appropriate Cext, and must with the VRNG coordination.
when (2)2 foot band switching control electric potential VRNG, 3, 4 foot external connection electric capacity Cext is invariable, 13 foot electric potential VFC is higher, the output signal frequency is higher.
(3)13 foot electric potential VFC is invariable, when 3, 4 foot external connection electric capacity Cext2 is invariable, output signal’s frequency is controlled in 2 foot band switching control electric potential VRNG height. When VRNG high electric potential. fo is low; When VRNG low electric potential: fo is high. Both difference’s scope is decided by VK.
Obviously, 13 foot electric potential Vfc use achieves the fixed condition from MCl45163P and LF control signal dynamic control VCO; 3rd, 4 foot external connection capacitor Cext should take the appropriate capacitance value: Like this uses 2 foot band switching control electric potential VRNG the height, may realize the fo frequency coverage area quite easily.
3.4 electric circuit schematic diagrams
Front the synthesis analysis, may obtain the electric circuit schematic diagram which as shown in Figure 7. Turns on MCl45163P the crystal oscillator is 2.048MHz, if RAl, RA0=01 are the frequency division ratio are 1024, then the hall hypothesis is 2kHz. 4 BCD codes, the N frequency division connection uses the unit electric circuit which shown in Figure 5, but establishes convenientlyⅣThe value, and may demonstrate the current BCD code by the nixietube the decimal digit, is also the current PLL frequency synthesizer’s output frequency (the unit: kHz). VC() external connection electric capacity Cext was schematic diagram 7 C12 only gives has accommodated the value scope, the concrete value should act according to the VRNG signal coordination which VC~) the actual output frequency and under mentioned to select. The VCO Y out-port through the electric capacity alternating current coupling to the MCl45163P 1 foot, after passing through its internal N frequency division, compares with fr, and by 13 foot PDout output, passes through the integral low pass filter which R8 and C11 are composed to obtain control voltage Vfc again to meet finally in the VC0 4 feet. The VCO 8 feet output the signal delivers to the l/2 frequency divider frequency division and the reshaping, the output signal frequency fo’。
May process like this regarding VCO frequency band control pin RNG: Through the integrated value comparator to BCI) /N frequency division highest order D3 carries on classifying, for example may through DIP switch hypothesis value comparator datum BCD (: B3 BO) is 0100 or 0011, when after D3 is smaller than or surpasses the datum, obtains Gao Huodi separately the electric potential VRNG signal. VRNG turns on VCO 2 feet, realizes the entire frequency range cover. Otherwise under the fixed VRNG invariable premise, VCO is unable to realize the frequency range cover, only if requests to output the frequency range not to be wide finally. And in VCO frequency shift scope.
3.5 measured data
(1) selects Cext (Figure 7 C12) is 33pF, value comparator datum B3 a B0 establishment is 0011, survey output signal fo’, and with nixietube demonstration value contrast, when 0.7MHz~9.999MHz electric circuit locking. Actual surveys VFC and between the output frequency relations, see Table 4.
Figure 7
(2) selects Cext is 20pF value comparator datum B3 a B0 establishment is 0100, survey output signal FCo’, and nixietube demonstration value contrast, when lMHz~9.999MHz electric circuit locking. Actual surveys VFC and between the output frequency relations, see Table 5.
Table 4 VFC and output frequency relations
| Explanation | BCD highest order D3≤3(0011):VRNG high level | ||||||||
| The frequency selects f0′(MHz) | 1 | 1.5 | 2 | 2.5 | 3 | 3.5 | 4 | 4.5 | 5 |
| VFC(V) | 0.57 | 1.21 | 1.77 | 2.35 | 2.92 | 3.47 | 0.80 | 1.04 | 1.15 |
| Explanation | BCD is the top digit ≥4 (0100): VRNG low level | ||||||||
| The frequency selects fo’(MHz) | 5.5 | 6 | 6.5 | 7 | 7.5 | 8 | 8.5 | 9 | 9.5 |
| VFC(V) | 1.34 | 1.49 | 1.58 | 1.74 | 1.95 | 2.27 | 2.99 | 3.71 | 3.95 |
Table 5 VFC and output frequency relations
| Explanation | BCD highest order D3≤3(0100):VRNG high level | ||||||||
| The frequency selects f0′(MHz) | 1 | 1.5 | 2 | 2.5 | 3 | 3.5 | 4 | 4.5 | 5 |
| VFC(V) | 0.26 | 0.79 | 1.022 | 1.65 | 2.07 | 2.48 | 2.88 | 3.33 | 0.81 |
| Explanation | BCD highest order D3≥4 (0101): VRNG low level | ||||||||
| The frequency selects f0′(MHz) | 5.5 | 6 | 6.5 | 7 | 7.5 | 8 | 8.5 | 9 | 9.5 |
| VFC(V) | 0.95 | 1.03 | 1.09 | 1.21 | 1.37 | 1.5 | 1.69 | 2.08 | 2.41 |
3.6 actual measurement results
after 4 BCD establishments, the nixietube demonstrated the decimal base value and the signaling frequency which surveys with the frequency meter consistent, confirmed the electric circuit to be at the fixed condition, front simultaneously satisfied the nixietube which mentioned to demonstrate that the BCD code correspondence the decimal digit was the current PLL frequency synthesizer’s output frequency.
