Speaking of based on the digital signal processor (DSP) system, the optimized power loss is one item important, but often with difficulty realizes project objective. Now, unified frequently based on the DSP equipment formerly respectively the independent many applications, each application possibly has many working patterns. Must obtain this kind of equipment’s power distribution is a very difficult matter, idle talk entire complex system. The designers need to learn that as far as possible many best information, as well as can help them to optimize power loss of the specific application technology and the tool.
What is lucky, in recent years, in the DSP chip’s design and the fabrication technology aspect, unceasingly was promoting a more advanced power loss to reduce the method. On present’s piece the power optimization techniques can provide more fine controls and the more province electricity pattern, as well as about processor power loss more complete information. The renewal DSP development kit enables the designers to understand thoroughly thoroughly system’s power dissipation way, and the hardware provides the power loss through the piece on to reduce the technology.
In order to let the development personnel be able to control the province electricity technology nimbly, was well coordinated during the numerous piece on functions the low power work and the succession question, the DSP operating system conformity many power management function. In these the accomplishment can and the tool adds on the system design the careful deployment, the DSP system’s power loss may obtain reduces large scale.
Low power loss question
The low power loss is very important to all DSP system, because although the reason applies specifically, but different. In the grid power supply system, the derate means that reduces the expenses, to enhance the reliability, as well as realizes the compact design, thus may integrate more functionalities in the same space, simultaneously need less ventilators and other cooling technology. In key application products and so on high clear in medical image formation, the quantity of heat which the component work produces even possibly causes the operation troubles, therefore, is lower than the equipment most large quantity definite value and increases to the low power loss request is very important.
In the portable electronic system, the low power loss is helpful to reduces system’s size and the weight as far as possible, after simultaneously delays until the battery charge’s period of revolution is longest. Compares small battery’s use to be possible to further reduce system’s scale. A lower power is also helpful in avoids the portable system in time delay use period overheated. Because the power loss reduces, handset, PDA, MP3 player, digital camera and video frequency camera these electronic instrumentation and other handhold equipment’s size day by day tenuous, the operating temperature is getting more and more low, but after charging the period of revolution to be getting more and more long.
Understands the power distribution and the chip resources
In any type’s system, the derate first step understood that system’s use way, how as well as this kind of use does affect the power loss. For instance, the handset majority of time are in the waiting call’s condition, the actual telephone conversation’s time are quite few. On the other hand, the MP3 player is usually not starting is at the activation running status, is at the shutdown condition. Other systems, the line power supply system as well as the portable system, have different wait for an opportunity the power loss distribution and the activation work power loss distribution, see also the following chart 1.
Figure 1: The work power loss and waits for an opportunity the power loss
Understood that the power loss distribution is helpful in the designers chooses a power efficiency the processor, because in certain type’s application, the DSP basic CMOS technical possibilities has the very tremendous influence to the power loss. Advanced CMOS craft based on working voltage extremely low high performance transistor. According to decides the application, may measure the body custom make transistor, through carries on the clamp to the quiescent current to drop to the power loss is smallest, or enhances to a big way the performance, although like this will increase the leakage current slightly. Specially DSP which designs for the handset such standby time very long application, may through divulge the transistor to drop to lowly the quiescent current lowly, but to always be in DSP which the state of activation the high performance application designs to favor a shutter speed quicker transistor.
The system use also includes the system to each kind of event’s response, as well as time closed circuit power source’s detention. On when initial electricity possibly has some detentions, when the system from waits for an opportunity the pattern awakens, the small detention is acceptable. But the user expected generally is at the activation active status the system to be able the immediate response, therefore on the piece the function could not be in the deep sleep pattern by now. Here has two aspect considerations: First, the partial functions may compare other functions to shut off thoroughly, particularly waiting for an opportunity period, activation duration of work also so. Second, processor’s power mode control ability is finer, the designers more can carry on the full power loss adjustment to suit system’s operation situation.
The high power efficiency’s DSP chip design through the establishment power source territory, enables the application not to shut off in the use function clock input, thus considered all these factors. Just like the processing essence can enter the sleep pattern, this time it does not carry out any operation, until is awakened by the signal of stop, the peripheral device and the memory module also similarly may put in the sleep pattern, when need is awakened. In the non-clock input function’s transistor except the quiescent current outside, does not have what power loss, but restores the clock to awakens the detention to reduce to is smallest. The system design personnel when consider its product the service condition, but also needs to consider in provides the clock aspect for each function, DSP can provide how many control, or whether can the automatic reduction.
Conserves energy another function which in DSP constructs is can adjust the core voltage and the frequency. If DSP might cut the core clock rate and still satisfy its processing request, then the work power loss will save in proportion correspondingly. A lower frequency adds on the lower working voltage, may save the quite considerable energy. May when the system initiation adjusts the voltage and the frequency is suitable for overall system’s movement, may also when the application needs to change gives the dynamic control through the software to it, this reduced for the non-peak value processing period’s power loss has provided one important method.
Correct power information acquisition
The complex DSP system possibly has many essences, the application and the management pattern, this causes to the power estimate to be extremely difficult. The traditional power determined that the method realizes based on certain information, for instance in the component data book indicates maximum current value, every week time or each instruction power consumption (mA/MHz, mA/MIPS) as well as test case and so on.
These methods can only use for to make the sketchy estimate, but speaking on the essence, the peripheral device and the piece the memory may carries on the independent switch’s complicated system according to the application and the operator schema, is insufficient to estimate the DSP power loss. The designers need to understand in clearly the practical application on the piece each function concrete power loss, because the actual power information enables them to estimate precisely realizes the plan result differently, and how determines the application is to affect the power loss in the different platform.
In DSP manufacture aspect, what needs is the modular power estimate plan, namely divides the equipment into certain subsystems, then moves independently each sub-system. Once had determined on each piece the function greatest performance number and the idle performance number, may be a function establish a power loss curve through the interpolation. Therefore, after having been clear about each function movement rank, may the performance number accumulation which obtains from each curve, finally gives the entire equipment’s actual power estimate.
Figure 2 is a power estimate electron data sheet, it decomposes typical DSP into certain sub-systems, by the user input related parameter, then may return to equipment’s power estimate. Looks like, estimates whether to be decided the information which correctly in the user who this electronic data sheet demonstrated provides whether to reflect to the system use way good understanding, including data width, frequency, in supply voltage and use peripheral device available bandwidth factors and so on percentage.
Figure 2: Power loss estimate
Low power loss design
Has the power loss consciousness design (Power-conscious design) the technology to be possible to help the DSP designers to use the correct power estimate fully. In the system-level, the designers should choose the related part carefully, causes its number as far as possible low. In addition, the designers should also consider which use the part hasn’t been possible to put in the province electricity pattern, particularly waiting for an opportunity period. The board level memory’s use is also a power dissipation source, because must simultaneously give the memory chip and the circuit wafer pathline power supply.
Using should use DSP as far as possible the internal memory, maintains on the piece the great band width saves, retains the exterior memory serves as the occasional low speed deposit. The piece external memory may also complete the start work well, but should after the start is put in the province electricity pattern. In order to reduce in memory’s code quantity and takes the instruction quantity, should optimize the software promotion performance. A more compact code is helpful to uses the buffer and the built-in command buffer well, moreover the running rate is quicker, can therefore reduce the system to be in the activation pattern the time.
The majority specific equipment use DSP to construct the hardware ability to reduce the power loss. From a start start, may let the module which using the equipment does not use be at the idling condition, the peripheral device power loss only limits uses in these assigning I/O which the time only then needs. Using usually when start on positive governing each module, later, which functions the DSP essence can the backstage carry out a circulation to examine not to need, then shuts off them. If applied has used these technologies, the chip sleep pattern might drops to the idle period essence and the chip power loss lowly.
If requests the overall performance is not equal to equipment’s complete ability, then may in the start time (V/F) carries on the adjustment to the DSP essence voltage and the frequency. If system in has the different performance load application to change, the V/F adjustment may also in movement period dynamic carries on. Must realize the V/F adjustment, the design essential provides the DSP external power supply voltage control, as well as in constructs at the backstage cyclic program software control. Because the frequency control reduces speed the essence the running rate, the designers should consider the incident cross-correlation in the application design during each operation succession question.
In OS power management
No matter comes the dynamic change system’s power request through the V/F adjustment through the low power loss pattern, needs to involve to DSP real-time operating system (RTOS). In the RTOS power management (PM) module can when the start realizes the power loss to save, and is coordinated each low power loss operation on the overall system.
The essence frequency control can affect the succession which the subsystem operates, therefore PM can after completing the frequency control carries on the clock adjustment. If corresponded uses for saying that the OS clock precision was unimportant, or was the user hopes to save the space, then might not use the PM function
In addition, when the thread blocks, the user may also activate or stop using automatically causes the clock to be at the idling condition the PM function. In its coordinated function, PM provided one kind to use in the power event notice the registration function, when the specific power management event occurred, the customer might register the notice, as a result of system’s complexity, PM supported many client sides and permits customer detention event’s completion.
PM has also provided a application programming interface (API) storehouse, may realize the chip low power technology software control. Through these API, the application can the gating clock, activation sleep pattern and the safety control V/F adjustment establishment between transistor. These establishment achievement adjustment parameter, enables V/F to defer to the correct order to reduce and to enhance, and has the establishment time which the proper operation must.
The following chart 3 had demonstrated how the establishment spot is controls the V/F adjustment the succession. Because the voltage and the frequency control to designs DSP which and the voltage regulator uses is specific, PM a API support establishment detention inquires and disposes, simultaneously the PM storehouse may reconstruct.
Figure 3: Power loss adjustment result
Tool’s auxiliary development function
Wants the effective addressing above all technical question, needs some specially the tool which designs for the power management. Is similar in DSP tool development other domains, the power optimization tool also devotes in provides the superiority which the visualization and easy to use, helps to simplify the system analysis and to reduce the going on the market time.
These tools unify DSP embedded and the RTOS power management technology, may provide gauge table, oscilloscope profile, channel calibration, test code and event triggering and so on test functions. Using these convenient functions, the designers may obtain a feedback mechanism, realizes the plan one by one depending on this appraisal to the power loss the influence, obtains a preferred plan finally.
Figure 4 had demonstrated in design cycle, integrated hardware and tool platform, for instance national instrument Limited company (National Instruments) the C55x power source optimizes DSP basic suite (DSK), how can as well as appraises DSP in any place help development personnel under the different design environment the power loss, thus causes is they can designate rapidly most suits its system’s best low power loss/high performance overall concept.
Figure 4: Power loss optimization flow
From the very beginning carries on the power design
In the system development, the power optimizes is treated sometimes as an item the work to process afterward, but this is incorrect. In the development cycle, considered more early the power optimization question is better, speaking of has many applications and the working pattern complicated system as if is especially. In order to lengthen the battery operating time, the low power loss usually is one of main requests, even if is the line power supply system also needs through to reduce the power consumption to reduce the radiation and the run cost.
In order to optimize the power loss, the designers need to understand that system’s power distribution, provides the comprehensive reference information source, thus considers the power estimate all main system functions. Integrated the hardware technology based on high power efficiency’s CMOS craft DSP, for instance fine definition low power pattern and voltage/frequency control. API makes these technologies to be very easy through RTOS to realize the application control, the testing tool may help the designers to estimate realizes the plan power loss differently. Using these resources, the development personnel have the full reason most to start from the development cycle to carry on the power design.
