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Digest: This article described in detail (Texas Instruments) C55x in the series DSP platform integrated in TI real-time realizes 0.3kbps to arrange the decoding algorithm to the 16kbps many kinds of speed pronunciations the method, and optimized the assembly directive in the existing C language source code foundation the skill. Introduced in compiles C55x in the series DSP assembly program the key technologies, such as in function call’s parameter transmission, the instruction optimizes, flag bit establishment, great use and so on. The article simultaneously gave one kind to use TI C55x the series DSP design to realize can move many kinds of pronunciations to arrange the decoding algorithm hardware system platform. Finally introduced this hardware platform’s dynamic alignment power loss design, causes system’s power loss most to be low under the dormant state is only 155.1mW.

Abstract:This paper detailed describes how to implement the real time multi-rate speech encoding and decoding algorithms between 0.3kbps to 16kbps on TI (Texas Instruments) C55x series DSP platform, and introduces methods of optimizing assembly language instructions based on the original C language source code. We introduce the key techniques during writing assembly programs like parameter transferring during function calling; instruction optimizing; status bits setting and macro application. The paper also design a hardware platform for general speech encoding and decoding based on C55x series DSP of TI Company. At last, the adaptive power design of the platform is presented that which reduce power of the system down to 155.1mW when in sleep running mode.

Keyword: Speech Coding; C55x; Assembly language

In the recent 20 years, the global semiconductor industry’s swift development drives the related software, the hardware design level to enhance rapidly, these development cause a large quantities of performance fine complex digital signal processing algorithm to be possible real-time to realize and obtain the widespread application in the daily communications system, enhanced the existing communications system’s reliability and the efficiency enormously. Therefore, the research pronunciation processing technology and with realizes it based on the DSP chip hardware system has the very vital practical significance and the broad market prospect. This article introduced the pronunciation arranges the decoding hardware platform the design mentality and arranges the decoding algorithm in hardware platform realization with the optimal process, simultaneously has given the hardware platform structure and the low power loss design mentality.

1        In the platform the pronunciation arranges the decoding algorithm summary

This article realized 0.3kbps in TI C55x on series DSP to arrange the decoding algorithm to the 16kbps many kinds of different speed pronunciations. And the 16kps speed uses the continuous variable delta modulation (CVSD) the profile encoding algorithm, the 8kps speed has used ITU-T the announcement G.729a canonical algorithm. But the low gear rate arranged the decoding to use the sine drive linear prediction (SELP) the algorithm. The SELP algorithm is the establishment in the traditional linear prediction model foundation, the voiceless sound ingredient with the white noise fitting, the voiced sound ingredient in each overtone place with a frequency shift’s sinusoidal signal synthesis, the entire drive’s voiced sound part becomes by a group of different scope’s sine superimposition, this is also the SELP model is different with a traditional linear prediction unusual important aspect, namely the drive signal uses the minute belt mix sine drive.

2        The pronunciation arranges the decoding algorithm and optimizes on DSP digital processing chip realization

Because moves on DSP the sounder must meet the solid current events’ requirements, but direct compilation’s C procedure is unable to achieve far. Therefore needs to compile and optimizes C55x the assembly code to raise sounder’s operating efficiency. Following introduces several spots, in the algorithm hardware realizes in the process key technologies:

2.1 C procedures and assembly program being enrolled together, function transfer and parameter transmission

Rewrites a module for the assembly function, then transfers it in the C procedure or the assembly program. In the C55x development, the function transfer mechanism is this: First records the parameter which the minor function transmits, with return address SP to low displacement. Then starts out the space which again in the storehouse the local variable constant needs, SP once more to the low displacement.

(1) assembly function statement: Function which defines in the assembly function if, if wants to transfer in the C code, must use the .global sentence to state, like this, the object or the function are defined as exterior (external). For instance:

    .global _Rem_Dc

_Rem_Dc:

    ……

(2) parameter transmission: In function call’s process, the parameter which the C code transmits deposits according to the below rule in the specific register: Namely 16 or 23 data indicators, deposit successively in (X)AR0-(X)AR4. 16 data, deposit successively in T0, T1, AR0-AR4, 32 data, deposit successively in AC0, AC1 and AC2. If the parameter integer surpasses the register integer, then deposits in the storehouse. At the same time, function returns value, if is the short trueing (short), then deposits in T0, if is the long trueing (long), then deposits in AC0, if is the indicator deposits in (X)AR0.

For example:

①int fn (int i1, long l2, int *p3);

Then fn->T0; il->T0, l2->AC0, p3->AR0

②long fn (int *p1, int i2, int i3, int i4);

Then fn->AC0, p1->AR0, i2->T0, i3->T1, i4->AR1

③void fn (long l1, long l2, long l3, long l4, int i5);

Then l1->AC0, l2->AC1, l3->AC2, l4-> storehouse, i5->T0

④void fn (long l1, long l2, long l3, int *p4, int *p5, int *p6, int *p7, int *p8, int i9, int i10);

Then l1->AC0, l2->AC1, l3->AC2, p4->AR0, p5->AR1, p6->AR2, p7->AR3, p8->AR4, i9->T0, i10->T1

2.2 flag bit establishments

    The flag bit is the DSP chip when the computation establishes some positions. They deposit in ST0_55~ST3_55, mainly uses several in the operation to include:

    FRCT, when its value is equal to 1, multiply operation’s result will shift to the left one. Is equal to the zero hour, the operation result is invariable.

SATD, when its value is equal to 1, the operation has when the overflow full and processing

SXMD, when its value is equal to 1, the input operand has the mark expansion

SMUL, when its value is equal to 1, the saturated pattern opens

They save separately in ST1_55 and ST3_55 register’s position as shown in Figure 1:

Figure 1 C55x DSP essential flag bit in register position

    These operation position’s establishment incorrect words, will present the operation result the mistake. Must therefore need to establish the operation position correctly according to the procedure, simultaneously must protect in procedure around and return to original state its starting value.

psh * (ST1_55)

psh * (ST3_55)

……

pop * (ST3_55)

pop * (ST1_55)

3        The pronunciation arranges the decoding hardware platform summary

This article designs the multi-pattern pronunciation arranges the decoding system based on C55x series DSP and the MCU dual processor design, the main chip has used TI Corporation’s TMS320VC5510A digital signal processor. Its clock cycle most is high is 200MHz. Has on the 160KWord piece RAM (includes 8 4KWord DARAM and 32 4KWord SARAM), on the 16KWord piece ROM, the 8MWord biggest expansion addressing ability. The micro controller (MCU) selects TI Corporation’s MSP430F149, mainly completes the system initiation, the power source management, the condition monitoring, the DSP program load, functions and so on sounder binary system symbol stream position rearrangement, and coordinates with DSP to realize the system-level encryption mechanism. Moreover, hardware platform’s audio frequency arranges the decoding chip to select TLV320AIC10, what but the procedure memory part uses is SST39VF160 Flash, the capacity is 1MWord, uses for to store up the procedure and the data. This hardware platform’s frame structure drawing as shown in Figure 2.

Figure more than 2 speed pronunciation arranges the decoding system hardware platform frame structure drawing

4        Low power loss design

In the digital integrated circuit design, the CMOS electric circuit’s static power loss is very low, compares basically with its dynamic power loss may ignore, therefore did not consider temporarily. Its dynamic power loss formula is:

             　　(1)

In the formula Pd is the CMOS chip dynamic power loss; CT is the CMOS chip load capacitance; V is the CMOS chip working voltage; f is the CMOS chip operating frequency. This hardware platform’s low power loss design from selects has the variable voltage and the multi-voltage component, the dynamic power loss management, the dynamic frequency control three aspects obtains.

4.1 select has the variable voltage and the multi-voltage component

    First in the article system, monolithic integrated circuit chip TI Corporation’s MSP430 which selects series MCU is a section of power loss quite low component, power line voltage 1.8V~3.6V, under the movement pattern the power loss 280μA/MHz, waits for an opportunity under the pattern the power loss 1.6μA/MHz, is forbid under the pattern the power loss 0.1μA/MHz. Next selects DSP chip TI C5510 DSP uses two kind of slaving voltages, essence voltage 1.6V, I/O voltage 3.3V, according to (1) the formula, IC component’s power loss and power line voltage’s square is proportional, the 1.6V power supply’s component can reduce more than 50% power losses compared to the 3.3V power supply component. In the IC design will usually reduce the voltage to take the control power loss the most direct method, through uses the low voltage power supply DSP, can also reduce the essence dynamic power loss effectively, but can also give dual attention to I/O the level compatibility.

4.2 dynamic power loss management

PCM arranges decoding chip TLV320AIC11 to be possible alone is forbid A/D or the D/A part. When microphone PTT has not pressed down, indicated that does not have the voice input, this time may a A/D mounted cylinder be the IDLE condition. Similarly, when MODEM CD signal for high, does not express the effective digital symbol stream input sounder, therefore in this time may a D/A splitting be the IDLE condition. Through disposes this chip the low power loss pattern, reduced system’s power loss. Moreover, C5510 the DSP chip interior delimited five independent IDLE territories, was responsible for CPU, DMA, CACHE, the peripheral device, the clock generator, the EMIF connection disposition separately. Each territory may establish independently this territory jurisdiction many parts the active pattern or the IDLE pattern reduces by this DSP the power loss. Designs in view of this article, because has not used DMA, CACHE, in the clock generator three territory peripheral devices, therefore established these three territories the IDLE pattern. EMIF territory in DSP and MSP exchange data (to adjust a bit class which transmits and receive) time is set for the activity, when other is set is IDLE. Through such establishment, has controlled overall system’s operation power loss effectively.

4.3 dynamic frequency controls

According to (1) the formula, the IC component’s power loss and the frequency are proportional, therefore, in just well satisfied the IC component’s frequency control the operation processing request the situation, may reduce the system power loss greatly. This method’s key is the algorithm operand size, dynamic adjustment chip movement frequency, thus achieves saves the power loss the goal. Designs in this article in the platform moves six speed’s low gear rate pronunciations arrange in the decoding algorithm, 600bps, 1200bps, 2400bps, 8000bps, the 16kbps peak value operand respectively is 37.4MIPS, 59.2MIPS, 44.8MIPS, 18.6MIPS, <1MIPS, therefore establishes separately the DSP operating frequency in 40.096MHz, 65.536MHz, 49.152MHz, 24.576MHz. Such processing can reduce DSP very effectively the essence power loss, maximum limit effective use operation resources.

Through the above several aspect’s optimization design, we have achieved the application situation to the power loss request. Table 1 is this system’s under different movement pattern power loss statistics.

Table under 1 different pattern DSP power loss

5        Subtotal

In this article introduced arranges the decoding algorithm in view of the pronunciation to realize the method in TI C55x on series DSP. Unified author’s summarized in the compilation assembly program main skill in actual performance history experience and the experience. At present the C55x high performance low power loss characteristic can sharpen portable equipment’s handling ability and battery’s service life large scale, widely will apply in pronunciation processing each domain. This article introduced the method and the experience have the broad promoted value.

This article innovation spot: 1. has pointed out many kinds in TI C55x in the series DSP platform the assembly language development experience and the skill. 2. realized one to be possible simultaneously to load many kinds of speed service pattern pronunciation to arrange the decoding the embedded hardware platform. 3. used many kinds of plans to realize to this hardware platform low power loss design, to a great extent saved system’s movement power loss.

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