0 introductions
The digital image processing technology obtained the widespread application in the electronic communications and the information processing domain, designs one kind of function to be nimble, the easy to operate, is advantageous inserts has the vital practical significance to system’s in video signal gathering electric circuit.
When research based on DSP video frequency supervisory system, considered the high speed real-time processing and the practical two aspect’s specific request, needs to develop one kind to have high speed, characteristic and so on high integration rate video image signal gathering systems, for this reason the system uses the special-purpose video frequency decoding chip and front end the complex programmable logical component (CPLD) constitution the image gathering part. Designs uses the special-purpose video frequency decoding chip, takes the control unit and the periphery connection by the CPLD component, take FIFO as the buffer structure, can realize video signal gathering and the read effectively high speed parallel, has the integrated circuit to be simple, the reliability is high, the integration rate is high, merits and so on connection convenience, do not need to change the hardware circuit, may apply in each kind of video signal processing system. Enabled the very complex circuit design to obtain the enormous simplification originally, and caused the original pure hardware’s design, turned the software and hardware’s mix design, made overall system’s design to increase the flexibility.
1 system hardware platform structure
System platform hardware architecture as shown in Figure 1. The overall system divides into two parts, respectively is the image gathering system and based on the DSP main system. The former is one based on the SAA7110A/SAA7110 video frequency decoding chip, realizes the precise sampling high speed video frequency gathering system by complex programmable logic chip CPLD; The latter is the general digital signal processing system, it mainly includes: 64K the WORD program memory, 64K the WORD data-carrier storage, DSP, the clock produce the electric circuit, the serial interface and the corresponding level switch electric circuit and so on.
System’s work flow is, first assigns the region by the image gathering system according to QCIF form precise gathering the video image data, temporarily stores in frame memory FIFO; Will temporarily store by DSP in the FIFO data reads in DSP in the data-carrier storage, carries on together with the original several image data based on the H.263 video data compression; Will then compress after DSP video data smoothly from serial interface output, transmits from ordinary MODEM or ADSL MODEM to the far-end monitoring center, after monitoring center’s PC machine receives the data, carries on the corresponding decoding, after and will return to original state the video image to carry on the demonstration or to carry on based on the WEB broadcast.
2 video signal gathering system
2.1 video signal gathering system’s basic characteristic
The video signal gathering system generally enlarges, the synchronized signal separation, brightness/parts generally and so on chrominance signal separation and A/D transformation by the video signal after the clamp is composed, the sampled data according to certain succession and the bus request, outputs on the data bus, thus completes the video signal the decoding, in the chart memory takes the frame sampling buffer storage, may adapt the different main line, the output format and the succession request bus interface.
The video signal gathering system is a high speed data gathering system’s exceptional case. Past video signal gathering system used the small scale digit and the simulation component, realized the high speed operation to enlarge, the synchronized signal separation, brightness/chrominance signal separation, the high speed A/D transformation, the phase-locked loop, electric circuit’s and so on sequential logic control functions. But because system’s sampling frequency and the work clock reach as high as dozens of megacycles per second, and the component integration rate is low, the wiring is complex, between the interstage and the component the coupling disturbs in a big way, therefore the development and the debugging are very difficult; On the other hand, to achieve the precise sampling the goal, the sampling clock needs with to lose person’s video signal constitution synchronization relations, thus, the use separates the synchronized signal and the systematic sampling clock carry on the phase-lock, produces the precise synchronized sampling clock, becomes in the design and debugging process another difficulty. At the same time, before realizing the programmable control which brightness, the chromaticity, the contrast gradient, the video frequency the level enlargement increases, achieves video signal gathering the intellectualization, is also the former system completes with difficulty. About this point, had in the system initial period performance history realizes [1] sincerely.
Based on the above consideration, this system used SAA7110A to take front end the video frequency supervisory system’s input the video frequency sampling processor.
2.2 video image gathering system design
SAA7110/SAA7110A is the high integration rate, function perfect large-scale video frequency decoding integrated circuit [2]. It used the PLCC68 seal, the interior integrates 2 8bit mold/number switch which the video signal sampling needed, the clock has produced peripheral circuits and so on electric circuit and brightness, contrast gradient, degree of saturation control, substituted the original discrete circuit with it, reduced the system design enormously the work load, and realized the function nimble disposition through the built-in massive function electric circuit and the control register. SAA7110/SAA7110A may the application scope including the tabletop video frequency, multimedia, domains and so on digital television, imagery processing, videophone, video image gathering system.
The SAA7110/SAA7110A control bus connection is the I2C main line. SAA7110/SAA7110A as the I2C main line from the component, according to the SA base pin’s level, component’s read-write address may distinguish the establishment is 9CH/9DH(W/R, SA=0) or 9DH/9FH(W/R, SA=1). Its internal total 47 registers, control the decoder separately (00H~19H) and the video frequency connection (20H~34H). Reads, writes the internal above register through the I2C main line, may complete functions and so on input channel choice, clamping and gain control, brightness, chromaticity and degree of saturation control.
But, some question must solve, that is the DSP chip does not have the built-in I2C bus interface, for this reason, this system proposed and uses pin has carried on the software simulation to DSP the chip two programmable I/O to realize the method which the I2C main line controlled. Because is most greatly only had the C2000 procedure storage space the 64KB limit, to reduce the I2C main line control simulation software’s scale, the simulation software uses the assembly language to complete completely, thus has brought the suitable difficulty and the work load for this system’s design.
3 system experiments and simulation
In real time system’s design, the synchronization and the precise sampling are two very important questions, their direct relation system design success or failure.
As a result of SAA7110A output two clock signal LCC and LCC2 and sampling clock and data output clock synchronization, thus may take in the sampled data interface control subsystem the data storage control clock and completes each kind of function the synchronized clock, the system does not need to regenerate or uses other clock signal, thus has avoided the external clock, the sampling clock and the video signal synchronization and the phase-lock question, both has guaranteed overall system’s synchronization, and reduced the system design order of complexity enormously. By SAA7110A output line desired signal HREF, good synchronized signal HS, field synchronizing signal VS, odd and even field signal ODD, as well as systematic sampling clock LCC and 1/2 frequency division clock LCC2 and so on undergoes processing, may obtain the current sampling positional information, and with produces the frame memory address, to select patches or strips of land as worth saving for seed and to write the control signal to realize the sampling time, the space position and the precision request together.
Reads the succession according to the DSP chip (as shown in Figure 2), writes the succession, SAA7110The chip HREF signal succession, the Vertical signal succession (as shown in Figure 3) and the Horizontal signal succession request, according to gathers QCIF(176×144) form image the need, designed the CPLD precise sampling sequential logic (as shown in Figure 4).
(b)
Figure 4 CPLD succession simulation chart
(a) CPLD precise sampling sequential logic; (b) carries on 32 time of enlargements to figure above (b)
CPLD which obtains after Figure 4 the succession simulation result, has met the predetermined precise sampling requirements completely. Realized truly had the correct proportional relationship precise sampling, the effect is good.
4 conclusions
In based on the DSP video image gathering system design, uses the video frequency special-purpose to decode a/D chip and complex programmable logical component CPLD carries on the control and the connection part design can realize video signal gathering and the read effectively high speed parallel, has the integrated circuit to be simple, the reliability is high, the integration rate is high, merits and so on connection convenience, do not need to change the hardware circuit, may apply in each kind of video signal processing system. Enabled the very complex circuit design to obtain the simplification originally, made overall system’s design to increase the flexibility.
Reference
1 Sun Jiping, Guan Yong. DSP extremely low code rate mine pit long-distance video frequency supervisory system [J]. Xian University of Science and Technology Journal, 2003,23(3):283-286
2 Philips Semiconductors. SAA7110/SAA7110A Data Sheet[EB/OL], 2001
