The embedded software development needs has the widespread thorough understanding and the understanding to the goal construction and the use. Transforms the embedded system from the concept for can effectively the highly effective solution which deployed in the hardware environment, needs a series of steps. The entire process includes: Analysis, construction build, appraisal, hardware support, design, code, debugging, integration, confirmation and confirmation. In this process, if the hardware source has not obtained the effective use, perhaps the software has not carried on the optimization in view of the hardware source, possibly has the serious influence to the performance.
CEVA-X in the series DSP essence uses the innovation construction needs the completely novel plan, to control the overall performance by the full use possible design variable. CEVA-X1620 is the CEVA-X essence series first model of product, uses the very advanced parallel construction, may carry out in a machine cycle reaches 8 instructions. Regarding this kind of advanced construction, the high efficiency and the high efficiency use hardware source is important.
In addition, the CEVA-X conformity complete memory subsystem, has been responsible for the lamination memory management. This includes the direct access to visit on the (DMA) controller, the board the buffer, to read in the buffer, the internal and the exterior memory, the memory management and the arbitration. Using this kind of widespread function collection, through the complete precise simulation environment and advanced disposition ability, may with ease complete the software application the optimization.
To simulation environment request
Speaking of based on the DSP/real-time software development, the simulation environment is important, needs to have the following several characteristics.
Viewability
The transparency - - may monitor the internal hardware and the hardware logic work. Even if they are not a hardware interface part, is not generally obvious in the actual hardware environment, but, understood that their situation is solves the problem and enhances the performance the key.
Debugging - -, when lacks the precise simulation environment, in only provides on the limited viewability hardware to move all advancements to mean that needs to use more resources, and will increase the debug time. Therefore, the simulation environment should provide the extra debugging function which the hardware itself does not support.
Flexible - - this is refers to before the submission for the final system construction inspects several kind of different system layouts ability. Realizes the optimum performance usually to establish the different hardware environment parameter, and carries on the repeated test using the software. Regarding concrete establishment which chooses, needs to depend upon the simulation environment to come perfect forecast it to the system the influence.
Time - - before can carry out all running time test, does not need to cost the too much time and to increase the special hardware to be able to realize the parallel hardware and software’s development.
Precise simulation and comprehensive disposition
The advanced simulation and the disposition environment use the software modelling completely, and has the comprehensive widespread disposition ability, can the help system construction teacher and software engineers DSP carries on the application design well. This method and the environment obviously enhanced the system performance, reduced the development time correspondingly. The comprehensive modelling environment means that CEVA-X1620 realizes the plan to be able to use in the different phase of exploitation or the different development goal by many kinds of patterns.
Simulation
In what the tool supports first is similar to the standard simulation solution basic set of instructions simulation (ISS) pattern. In this kind of pattern, each instruction takes the inalienable stage to carry out. This pattern carries out the speed to be quick, is advantageous for the software development.
Cyclical precise simulation (CAS) is the more advanced simulation pattern. In this kind of pattern, including all assembly line level construction behavior by complete simulation. When carries on the curacy checking or the hardware confirm, this pattern to the entire system simulation is important, by now the simulator might simulate the real hardware’s function conveniently as the essence module. Besides the cyclical precise ability, complete memory subsystem (MSS) by the modelling, may carry on to the overall system the simulation. As the matter stands, as a result of software and hardware’s correlation, can therefore realize the real precise simulation. This kind of pattern has included all MSS module, therefore may carry on the debugging to all memory hierarchy, including the buffer, writes the cushion, the internal/exterior memory. Moreover, it may also through the simulation analysis different memory layout situation, aim at each kind of layout, the observation algorithm execution period memory’s visit and the conflict situation.
Disposition
Besides comprehensive consummation’s simulation ability, CEVA also provides face the C-level application procedure and memory’s configurator. This kind of configurator may carry on the automated analysis to the entire simulation environment.
It can provide the complete C-level disposition in the basic ISS pattern. Through searches the latent question, for instance the application essence, the bottleneck and most consume the line of code the part, but enhances the software performance effectively. This is the very powerful tool, can reduce the essential function the clock number and the non-essential function code size. The application procedure disposition is carried out automatically in the C function, does not need to revise any code, meanwhile may use in the assembly program.
Then, the application procedure disposition may is carried out based on CAS and the MSS simulator, by acts according to each function the memory mapping and the memory conflict obtains its true application performance.
In the application procedure is disposed after CAS and the MSS pattern and the related function already determined, the configurator may give the complete memory use information, including the buffer use and the conflict, each function stagnant outline, the code memory stagnates, the data storage to stagnate, the code memory conflict and the data storage conflict related information. This kind of comprehensive thorough MSS disposition information may instruct user’s in view of application in each specific function optimization memory use.
Conclusion
At present, this kind of modelling and the disposition flow successfully were already used in realize certain algorithm function code quantity simplification, and has assisted to use the chip set which the CEVA essence carries on designs finally to obtain the splendid performance numerously.
