Abstract: The COSTAS link is one kind of closed loop self-adaptive system, uses in withdrawing the coherent carrier. This article mainly introduced one kind uses in the carrier synchronization the higher order COSTAS ring circuit, uses in completing MPSK in the demodulation carrier synchronization. This article proposed one kind the COSTAS ring circuit’s simplified structure which is advantageous for the software to realize, uses in completing 8PSK the carrier synchronization, and discussed in detail has adopted the digital signal processor (DSP) to program realizes COSTAS ring circuit’s some questions.
Key word: COSTAS link, DSP, MPSK, carrier synchronization
1. Introduction
The MPSK modulation applies one of most widespread digital modulation ways. According to the signal detection theory, to select phase-locked loop’s coherent reception method to the MPSK modulation signal’s average error rate smallest optimum reception way. But, the MPSK modulation signal is the quiescent carrier signal, cannot use conventional the phase-locked loop or the narrow band pass filter withdraws the reference carrier directly. Moreover is different with some phase continual modulation signal, its carrier phase change can only take the limited several discrete values, explained in the modulation signal to contain the reference carrier phase information. May through misalignment processing, in the erasure signal modulating message, restore in the modulation signal the concealed intelligence signal, thus completes the signal the demodulation. At present, the commonly used MPSK carrier restores the method includes: Square link law, phase-locked loop law and so on. In this article, the author has designed the new higher order COSTAS link, it has, the pull-in bandwidth big, to be able reliably to realize the synchronized merit fast.
2. Higher order COSTAS ring circuit’s principle of work and structure
Costas in 1956 first proposed that uses the synchronism - orthogonal link to restore the intelligence signal. Afterward, Riter et al. proved that tracks the low signal-to-noise ratio the quiescent carrier signal best installment is the COSTAS link and a square link. The COSTAS ring circuit is one kind of closed loop automatic control system, the traditional simulation COSTAS ring circuit, because synchronism leg and orthogonal leg’s imbalance, thus causes ring circuit’s performance to come under certain influence, and analogous circuit existence cocurrent zero drifting, debugging difficult shortcoming, but the entire digital COSTAS link may avoid the above shortcoming, and has the very strong compatibility based on the software radio principle’s COSTAS ring circuit.
2.1 ordinary COSTAS ring circuit’s principle of work and design
2.1.1 COSTAS ring circuit’s general principle
The COSTAS ring circuit including the discriminator, the ring circuit filter, the pressure controls the oscillator. The discriminator is a simple multiplier. Not only LF (ring circuit filter) can play low pass filter’s role in the COSTAS ring circuit, and has decided the COSTAS ring circuit’s performance parameter. Because the ideal second-order active ring circuit filter performance surpasses other ring circuits far, when locking the stable state difference is 0, the synchronization raises, this article uses the ideal second-order ring circuit, its digitized schematic diagram as shown in Figure 1.
Figure 1 COSTAS basic principle
in 2.2 heterogeneity signals withdraws the carrier
Has two phases regarding BPSK, the available above method withdraws the carrier. But commonly used MPSK has M to select, cannot use Figure 1 COSTAS ring circuit to withdraw the carrier, must use the heterogeneity COSTAS link.
Figure 2 four-phase PSK signal COSTAS link functional block diagram
3. Higher order COSTAS ring circuit’s DSP algorithm optimization
Looking from the above M=8 higher order phase-locked loop’s structure, the 8PSK signal enters the higher order COSTAS ring circuit, needs to use DSP to realize the Chinese red army soldier discriminator, the Chinese red army soldier low pass filter (filters out frequency multiplication component, obtains low frequency component) and the pressure controls the oscillator, the computation load is very huge. How carries on the resources reasonable disposition, to achieve the DSP real-time processing is the difficulty which the carrier restores, therefore needs to do the thorough research to the DSP procedure optimization.
When uses the C language carries on the DSP software development, generally first on PC machine to the algorithm carries on the simulation, then transplants the C language to the DSP platform. According to the development order, the corresponding optimized work also includes two parts: First, in simulation environment optimization; second, DSP goal environment further optimization. Following unifies TI Corporation’s TMS320C64x series DSP the C compiler, discusses in the MPSK demodulation concrete optimized work.
3.1 SIN/COS function table look-up algorithm
In order to enhance the algorithm to realize the efficiency, introduced when movement calculates the time expenses, should as far as possible some movements when calculates the parameter makes the search table or the constant value. Not only this is suitable for some quite neat parameter list, regarding some not neat movement’s time computation, for example in the high and low frequency conversion and VCO, with the carrier multiplication’s SIN/COS computation, might use writes the array, realized with the table look-up.
3.2 operation running water processing
DSP CPU uses the running water line structure. The DSP majority instructions are the monocycle instructions, but the skipping class instruction actually usually must consume the many machine cycles. May disassemble the multiple circulations, reduces carries on to the surrounding loop number of times the control transfer the time, fully assembly line which constitutes using the optimizer.
3.3 CIC honeycomb filter’s use
Replaces the low pass filter using the CIC filter, achieves the reduced fixed point multiplication and the additive operation goal, has solved the problem which the monolithic C6416 resources are insufficient. For example: In this article the carrier speed is 4800kHz, the sampling rate is 230.4kHz, the discriminator output high frequency frequency is 9600kHz, uses 48 step CIC to be possible to filter out the 9600kHz frequency component. As a result in position, therefore the filtration effect is good, is bigger than far. CIC filter each coefficient is 1, may realize using the additive operation needs the massive multiplications and the additive operation function, reduces to the DSP internal resources use.
3.4 data transmission EDMA way
In the modulation demodulation process, DSP and exterior between has the mass data the exchange, this part of optimized work influence system performance. C64x supports EDMA, EDMA is enlargement mode DMA, is one kind, in does not have CPU to involve in the situation reference to storage’s way, namely by EDMA controller control data outside L2 memory/buffer and internal integrated peripheral device and piece between equipment’s transmission, but simultaneously CPU may parallel execution other instructions. EDMA is one effective data transmission way, may effective reduced EMIF operate the resources which under CPU needs.
Realizes the method to be as follows specifically: Decides BUF in the internal data memory block the length, and the one divides into two, may suppose is BUF1 and BUF2. In EMDA BUF1 and BUF2 are and so on memory sizes. In the data frame synchronizing signal’s rise along, DSP reads a data by the EDMA way from exterior to BUF1; Simultaneously in the BUF2 data carries on MPSK the demodulation algorithm. Likewise, in the next data frame synchronizing signal’s rise along, DSP reads another data by the EDMA way from exterior to BUF1. After BUF1 reads fully, DSP carries on MPSK to the BUF1 data the demodulation algorithm, simultaneously BUF2 carries on the data to read the operation, realizes the EDMA pingpong processing.
4th, higher order COSTAS ring circuit’s DSP realizes the result
This article selects 8PSK the mark speed is 2400kbps, the carrier speed is 4800kHz, the sampling rate is 230.4kHz. Shown in Figure 2 two groups signals respectively are observe using the CCS development kit’s observation window, extraction frequency synchronism intelligence signal and 8PSK modulation signal.
Figure 3 restores the intelligence signal (on) and receives baseband signal (next)
Figure 4 before 8PSK receiving end demodulation, star map chart (AWGN channel, SNR=17dB)
5. Concluding remark
This article mainly introduced one kind of new being suitable in MPSK carrier extract’s higher order COSTAS ring circuit, can satisfy the MPSK demodulation the need, and is advantageous for DSP to realize. Real-time realizes the question in view of COSTAS link algorithm’s DSP, has carried on the detailed discussion. Finally, has the high data rate 8PSK modulation demodulation example in view of one, has completed on monolithic C6416 based on the higher order COSTAS link’s carrier synchronization and the demodulation, and gave DSP which observed through the CCS tool to realize the result, proved that the higher order COSTAS phase-locked loop had the good carrier synchronization performance.
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