Abstract: The design development “the missile simulator embedded module” is the success completes a core link which some product design finalizes. The article introduced that system’s design demand is a starting point, joins difficult question which in the software and hardware performance history meets, the target-oriented summary in has established the embedded system hardware frame, the ARINC429 communication connection design, the FPGA logical design, as well as process and so on embedded software development and timely optimization some experiences and the technical way. Specially when design system outage service routine, creative proposed depends on the hardware platform under the fixed-point DSP environment to realize highly effective value operation certain methods, regarding satisfies aspects and so on system timeliness processing request to have certain application value.
Key word: Missile simulator; DSP; Embedded software; Real-time processing
0 Directing Word
In some new airborne weapons system’s triturating, the achievement guaranteed that the Readiness force grasps the new equipment to form the battle efficiency as soon as possible the key aspect, needs to design one kind to be able to serve the test training purpose the missile simulator. But this system design’s core duty is develops a set to be able to simulate produces carries on the synchronization ARINC-429(HB6096-86) exchange of information, the transmission telemetered data, the simulation with the missile-mounted flight control module to produce the sequential logic control signal, the establishment breakdown code and can carry on fault mode processing and so on a series to carry on the test training work to the product the embedded module.
1 System frame design
As a result of this module for the model missile-mounted embedded system, the use space is limited, the environmental condition is harsh, both requests the systems operation stable reliable, and the request has the strong data operation ability. The overall evaluation design demand, decided that the use “the DSP programmable logic component 429 communication connection signal match and the recuperation fault simulation installment” takes system’s hardware overall frame. As space is limited, this article only on the DSP expander, 429 communication connections as well as the FPGA logical function introduced. System hardware functional block diagram as shown in Figure 1.
Figure 1 system hardware functional block diagram
1.1 DSP and expander design
Selects armed forces grade SMJ320F240 which the TI Corporation 98 years promote digital signal processor [1], definitely may undertake the embedded module control processing core duty under the highly effective software algorithm’s coordination.
SMJ320F240 expander including clock circuit, reset circuit, data-carrier storage expander. SMJ320F240DSP internal RAM is 544 bytes, to satisfy the system request, outside expanded 32K DRAM, DRAM on the computer board to use cycrsj Corporation’s cy7c199-25DMB, the capacity is 32K, 8 bit data, the reading duration is 25ns, two piece of 32K, 8 bit data memories put together is 32K, 16 bit data memory through the 72LS00 decoding circuit, decided as high 32K the 32K16 bit data memory address space, namely 8000~FFFF.
1.2 ARINC-429 communication connection design
Speaking of the general 429 communication connection’s design method, usually uses pair of mouth RAM to take transmission path’s data buffer. But this design method is not suitable for this system. Because the above design method had only considered data batches of live transmissions, namely 429 transmit each data is 20×32bit, the pair of mouth RAM buffer generally is very big, on the lower half may store many data and batches of reads separately, is unable real-time to carry on processing to each data, does not conform to the exchange information agreement to each frame number according to the facts when processes this request.
In view of system’s design demand, uses the new design mentality, sets up take F240, FPGA, DEI1016[2] as skeleton’s intelligent communication interface module. FPGA selects Altera Corporation’s EPF10K20RC208 component, opens the suitable buffer using the VHDL compilation logic module to provide the real-time transmission for the data frame the platform, the data transmission operation completes the data depending on the FPGA logical program in the backstage the transmission receive, CPU completes data processing [3] in the onstage.
The data communication module’s control logic I/O which provides by F240 operation signal IS and read-write signal RD, WR as well as address A2, A1 is inputs is DEI1016 produces the operation signal. The control logic and F240 simultaneously monitor DEI1016 RX1RDY, RX2RDY, TX429RDY and so on 3 status signals to supply the software inquiry and to have the INT interrupt request by the control logic.
1.3 FPGA logical design
After having determined depends upon the FPGA large-scale programmable logic component takes F240 and the DEI1016 real-time communication transmission link, the FPGA logical program division is 5 parts carries on the design: CPU interface module, 429 chip interface module, 429 data transmission buffer module, 429 data interface buffer module, 32 precise fixed time counter modules. Functional block diagram as shown in Figure 2.
a) CPU interface module: Acts as FPGA interior various modules and CPU (SMJ320F240) between main line’s bridge. CPU the data bus, the address bus, the control bus hangs in the CPU interface module, the CPU interface module selects in separately FPGA through the address decoding the different module and the CPU communication.
b) 429 chip interface module: The primary cognizance with 429 chip DEI1016 communication, the DEI1016 data bus, the control bus connects in this module, this module basis different work management DEI1016 control bus or responds DEI1016 the control signal, simultaneously through parallel data main line transmission (receive) DEI1016 data.
c) 429 data transmission buffer module: Is responsible to receive CPU to pass on treats the transmission the data and the transmission start command and passes to 429 chip interface module these data and starts 429 chip interface module the transmission succession. This buffer can hold 20 32 bit data.
d) 429 data receive buffer module: Is responsible to respond 429 chip interface module the receive data interrupt signal and the data which receives exists in internal RAM, CPU may inquire 429 data receive buffer through the CPU interface module already the data integer which receives, and may momentarily read in the buffer the data. This buffer can hold 20 32 figures.
Figure 2 FPGA logical design diagram
From this sees, transmits 429 data nearly not to occupy the machine-hour, puts in the buffer the data then. When receives 429 data, this process by the logical program in the backstage movement, does not take CPU completely the machine-hour, has provided the condition before the backstage different duty’s concurrent operation.
2 Succession software design
2.1 Movement environment
In the simulation debugging stage software movement in the CCS2000 integrated development environment, uses the WinTech simulator to debug through the JTAG simulation connection online simulation, the operating system is WinXP. In the fever records after FlashEEPROM, software movement on the F240 piece system.
2.2 Structure and detailed design
The succession software is the embedded module and even the entire missile simulator’s control core, completes to the operational missile logic succession control as well as to the breakdown response. The software work flow take the sequential control as the master line real-time dispatch, completes the system initialization, the fault recognition, the simulation spike input output in turn, simultaneously transfers the interrupt service to complete with flies controls module’s exchange of information. The software lasts foreword control, interrupt servicing and the failure test three units according to the modular structure division.
2.2.1 Interrupt servicing unit
Completes in the interrupt processing cycle conforms to the detection unit with to fly controls the module information swap agreement 429 intelligence transmission control, including 429 exchange information and telemetry information’s real-time transmission, the receive, the data pack, the bale breaking and processing, realizes with flies controls algorithm return route’s closing.
The interrupt processing cycle is refers to: Using the cycle is 30ms, the dutyfactor is 1:1 synchronized square-wave signal positive and negative level produces the interrupt control signal, comes the synchronizing information exchange process. In synchronized signal’s level 15ms action cycle, simulates the detection unit to transmit 20 information word compositions the telemetry information frame. The embedded module altogether has 60 to the telemetry system transmission’s information word. In synchronized signal’s negative level 15ms cycle, the embedded module with flies controls the module to complete 20 characters the exchange of information process.
Interrupt servicing unit operation flow as shown in Figure 3. 429 data receives, the transmission, the data pack, the bale breaking related algorithm module, as space is limited here no longer gives unnecessary detail.
2.2.2 Sequential control unit
Completes the missile normal test logic the control, including system initialization, precise fixed time, uses DSP the digital I/O resources simulation with other modules, equipment’s information crossing linking, D/A uses for to simulate the rudder angle of deflection feedback signal to give the equipment. And initialization function void TargetInit(void) has completed to DSP, the FPGA resources initialization (interrupt resources, system clock/timer resources, I/O port resources, memory and so on, FPGA buffer reset, register’s setting). The function SetTimerCounter(0) uses in the system timer reset, function void sleep (unsigned long time) uses in the system time delay, precision 1us. The succession test point’s condition interpret and the signal establishment depending on port resources’ read-write complete to DSP the I/O, has defined the signal port address and the displacement quantity in CPLD logical program SConIO.vhd.
2.2.3 Failure test unit
Completes installs 20 kind of code to the breakdown establishment the recognitions, this unit in flow processing is not independent, but is inserts to sequential control and in the interrupt servicing unit, surpasses the equipment distinction target according to the predetermined failure test flow output the related error message, processing flow as shown in Figure 4.
Figure 3 interrupt servicing unit operation flow
Figure 4 failure test unit flow
3 Question and key to the situation
When design debugging interrupt service, meets the prominent question is the disparity which the system timeliness request and CPU handling ability exists. Because the system synchronized signal interrupt is strict to 429 data transmissions and the processing time request, specially 15ms negative half period, not only need complete several hundred including the floating point parameter operation data real-time processing, but must manage 429 data the receives and the transmission. Looks like F240 such fixed-point DSP operation efficiency to be competent with difficulty obviously. Therefore, when design interrupt service module has taken the following measure:
a) In the interrupt servicing flow, the possible arrangement CPU inquiry buffer condition’s time spot, after treating the previous data which CPU will receive and treats the transmission the next data processing finished, then inquires the buffer data integer, met Man Houyou CPU to read carries on processing, thus has realized the receive data and the processing data concurrent operation;
b) The data transmission operation mainly carries on depending on the FPGA logical program in the backstage, CPU completes the data processing in the onstage;
c) When 429 parameter packs, bale breaking treating processes, makes the improvement to the frequent use’s binary weighting processing method, no longer transfers in C canonical algorithm storehouse math.h pow () the function, will displace from the definition shifting operating function, pow () is the general C trueing/floating point operation storehouse function, F240 transfers it to take the massive machine cycle inevitably, but the shifting function while will realize binary weighting function, the operating speed can actually enhance doubled and re-doubled.
For the proof measure’s validity, uses the DL716 digit recording instrument channels the level reverse change of state which produces in the synchronized signal positive and negative half period to carry on the real-time gathering survey for DSP two idle I/O, obtained the system time-consuming to see Table in the interrupt processing process 1 (to count has surveyed 6 time value). The test result indicated that the system in the synchronized signal interrupts negative half period the running time to reduce largely to 13.5ms about, not only ruled out the possibility which the interrupt and the data frame lose, and has satisfied the exchange of information agreement to the sequential control and the data processing request.
Table 1 interrupt processing time comparative table
|
|
Before taking the measure, |
After taking the measure, |
||||
|
The K2 interrupt cycle half period system consumes the time (ms) |
5.50 |
5.48 |
5.50 |
5.48 |
5.56 |
5.51 |
|
The K2 interrupt cycle negative half period system consumes the time (ms) |
61.8 |
59.8 |
60.2 |
13.49 |
13.56 |
13.52 |
4 Knot Theory
Promotes the use as the embedded system in the defense-related science and technology domain the typical model, this module present has succeeded applies in some missile simulator, had demonstrated under each kind of complex use environment the good performance, grasps the new equipment regarding the user to form the battle efficiency as soon as possible to have the very vital practical significance.
This article innovates the spot: Uses the DSP FPGA embedded system skeleton, follows on-board electronics regarding the volume and the performance design requirements, simultaneously takes measures and so on parallel processing and software algorithm optimization, has satisfied the system regarding the integration, the functionality, the reliability, the timely request.
Reference:
[1] TMS320F/C240 DSP Controllers Reference GuidePeripheral Library and Specific Devices[M], Texas Instruments, 1999.6.
[2] DDC Data Sheet (DEI1016 ARINC429 Transceiver) [Z] .DDC Inc, 2004
[3] Xu is joyful, in the Red Flag, Yi Fan. Designs the [M]. Beijing based on the FPGA embedded system: Mechanical industry publishing house, 2005
[4] The Miao ultramarine, Li Yonggang the .FPGA component’s discusses the [J]. micro computer information in embedded system collocation method, 2006,11:161~162
