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Uses DSP, PLD and ASIC realizes multispeed filter design comparison - 51RD the Chinese electronic net
Friday, November 28th, 2008 at 23:55 | No commentsCategories: EDA/PLDShort Content: Many communications systems must use the multispeed filter (multirate filter), the multispeed filter are refer to the output data speed and the data-in speed not equal filter, commonly used Yu physical interface like d/a converter (DAC) or modulus switch (ADC) connection place. When filter output data to DAC, user regular session choice interpolation filter, because it can produce more sampling points to cause DAC the output wave shape to be smoother; But when filter from ADC received signal, the user ... -
Accelerates ASIC/SoC the prototype project software technique - 51RD the Chinese electronic net
Friday, November 21st, 2008 at 22:12 | No commentsCategories: EDA/PLDShort Content: ASIC and the SoC component cost's gradual rise force semiconductor supplier must further develop each component's market to seek satisfaction the investment repayment. Day by day the growth software use has provided the effective mechanism for this reason, because increases the software content equated in more functions and the software change has provided the particular market product variation. This tendency caused over a million line of software codes appears in ASIC or SoC is also nothing unusual. The multi-essence's use ... -
Uses the new SRAM craft to realize embedded ASIC and the SoC memory design
Tuesday, November 11th, 2008 at 07:49 | No commentsCategories: StorageShort Content: The sharp weapon which has been in many embedded designs uses ASIC/SoC based on the traditional six transistor (6T) memory cell's static RAM memory block to realize the development personnel who uses, because of this kind of memory structure very suitable mainstream's CMOS technical process, not to need to increase any extra craft step. Like in chart 1a shows such, interwove basically the coupling latch and the active load unit has composed the 6T memory cell, this kind of ... -
Based on Astro tool’s ASIC succession analysis
Saturday, August 16th, 2008 at 08:28 | No commentsCategories: EDA/PLDShort Content: Abstract: In the present ASIC design, clock signal's quality is getting bigger and bigger to the synchronization digital circuit's influence. How to avoid the succession question in the adverse effect into design important challenge which creates to the electric circuit. This article mainly introduced in the logical design is noteworthy the important succession question which, as well as how to overcome these questions. Finally introduced carries on the succession analysis using the Astro tool the method.Key word: ASIC; Synchronization digital ... -
Designs LED with EDA the Chinese character trundle monitor
Tuesday, August 12th, 2008 at 01:57 | No commentsCategories: EDA/PLDShort Content: Abstract: This article mainly discussed has used the EDA tool to design the Chinese character trundle monitor's technical question. In the article first described based on the scene programmable gate array (FPGA) hardware circuit; Then studied on 8×8LED the light emitter diode lattice had demonstrated that the trundle Chinese character the principle, and gave described its function VHDL language programming based on ALTERA parametrization model base LPM; Finally for uses the EDA tool software processing to demonstrate that the data ...
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