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Altera FPGA, the CPLD study writes down_FPGA, CPLD, altera
Tuesday, January 12th, 2010 at 20:27 | No commentsCategories: EDA/PLDShort Content: 1. hardware design basic principle Speed and area balanced and principal of reciprocity: If a design the succession remainder is big, can run the frequency is higher than the design requirements far, can be possible to reduce the entire design consumption through the module multiplying the chip area, this is trades the area with the speed advantage to save; Otherwise, if a design's succession request is very high, the ordinary method cannot achieve the design ... -
I2C main line communication connection component
Monday, January 11th, 2010 at 10:03 | No commentsCategories: EDA/PLDShort Content: The I2C main line is one kind which PHILIPS Corporation develops simple, bidirectional, the two-wire system, the synchronized serial main line. It only needs two lines (serial clock line and serial data line) then in the connection between main line's component the pass-along message. This main line is the high performance serial main line, has functions and so on ruling which and high low speed equipment synchronization the multi-main engine system needs, the application is extremely widespread. At present ... -
Based on monolithic integrated circuit
Monday, January 11th, 2010 at 08:11 | No commentsCategories: EDA/PLDTags: CPLD, microcontrollerShort Content: Based on SRAM (static stochastic memory) may reshuffle PLD (programmable logical component) the appearance, the PLD logical function has created the condition for the system designer dynamic change movement electric circuit. PLD uses the SRAM unit to preserve the layout data. These layout data had decided the PLD internal interconnection relations and the logical function, change these data, also changed component's logical function. Because the SRAM data is volatile, therefore these data must preserve outside PLD component's EPROM, EEPROM ... -
Realizes the highly effective multi-serial port interrupt source under the CPLD management_CPLD, interrupt source
Monday, January 11th, 2010 at 06:07 | No commentsCategories: EDA/PLDTags: CPLD, interrupt sourceShort Content: In the last few years, after PC time's oncoming, had succinctly, highly effective and so on characteristic embedded systems to obtain the rapid development. Embedded technological development today already each kind of computer technology multi-level, various overlapping fusion in one. The embedded system sped up the industrial design advancement, reduced the development cost and the risk, the use is simple, the expansion is flexible, highly effective simplification, but applies conveniently in various industrial field. The interrupt request uses border ... -
Low voltage CPLD EPM7512A mix voltage system design_CPLD, EPM7512A
Monday, January 11th, 2010 at 00:21 | No commentsCategories: EDA/PLDShort Content: Abstract: Elaborates the different logic level connection principle in detail. Take low pressure CPLD EPM7512A as the example, gives in mixes in the voltage system's concrete design proposal. Introduction Along with microelectronic technology's swift development, the volume is smaller, the power loss to be lower, the performance better low pressure chip to emerge unceasingly. I/O level logic to 3.3V, 2.5V, 1.8V, even a lower direction develops. But for dozens of years, because the 5V power source's component has occupied ... -
I2C component connection IP nucleus CPLD design_CPLD, I2C
Friday, January 8th, 2010 at 21:51 | No commentsCategories: EDA/PLDShort Content: Abstract: According to the monolithic integrated circuit I2C serial expansion's characteristic, in EDA under the software MaxplusII environment, uses the AHDL language, establishes the IP nucleus. This design realizes using the state machine, while gives the design to explain in detail the IP nucleus the setup procedure, and downloads to the chip through the hardware experiment confirmation. As a result of the CPLD digit design structurization's tendency, will appear in view of CPLD different level IP (Intellectual Property) the nucleus. ... -
Realizes the monolithic integrated circuit and the ISA main line parallel correspondence with CPLD_CPLD, ISA bus, parallel communication
Friday, January 8th, 2010 at 16:54 | No commentsCategories: EDA/PLDShort Content: Abstract: Chip realizes the monolithic integrated circuit and PC104 with ALTERA Corporation MAX7000 the series CPLD between the ISA bus interface parallel correspondence, gives the system design method and the procedure source code. Including correspondence software and AHDL design part. Key word: CPLD ISA main line parallel correspondence CPLD (Complex Programmable Logic Device) is one kind of complex user programmable logic component, because uses connects the structure continuously. This kind of structure easy to forecast the time delay, ... -
CPLD actuation numerical code display circuit_CPLD
Thursday, December 17th, 2009 at 16:55 | No commentsCategories: EDA/PLDTags: CPLDShort Content: 1.1 display principles: Digital display tube as shown in Figure 1.1, nixietube each section is a light emitter diode, altogether has a~g as well as the decimal point dp eight light emitter diodes. In nixietube each diode's negative pole parallel in the same place, composition public negative pole end. Like the common cathode base pin earth, which base pin this time inputs the high level, the correspondence light emitter diode is lightened.omit image. Figure 1.1 digital display tube CL5461AS nixietube ... -
Based on TMS320F2812 video image gathering system’s design
Wednesday, September 16th, 2009 at 01:44 | No commentsCategories: DSPShort Content: The fast development's automobile industry carried the electronic products for the vehicle to provide the broad application market, like Che Zai "the infrared surveillance", "the back-draft radar" and so on video frequency supervisory equipments, have already brought for the pilot conveniently, also has brought the security. These supervisory equipment cannot leave video image gathering, but the video image gathering key link is the video signal AD transformation. The traditional video image gathering system uses the special image gathering chip generally, ... -
Multi-channel UART which realize based on ADSP-BF533 and EPM7160 interface circuit design
Friday, September 4th, 2009 at 07:50 | No commentsCategories: DSPShort Content: 0 introductions At present, in the digital signal processing technology, DSP CPLD is in the control interface design the quite commonly used way. Although however, AD-SP-BF533 has the asynchronous serial port, but this chip only then an asynchronous serial port, when in a system presents many UART connections, ADSP-BF533 appeared is helpless. Therefore, this article uses CPLD to realize the multi-channel UART connection design, satisfies ADSP-BF533 and the multi-channel UART connection correspondence. 1 ADSP-BF533 synopsis The ADSP-BF533 processor is in ...
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