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Tuesday, September 23rd, 2008 at 15:10 | No comments

Categories: EDA/PLD

Tags: Code error tester, digit phase-locked loop, discriminator, FPGA

Short Content: Abstract: This article designed realizes one kind to use in surveying the baseband to transmit channel's error code meter, elaborated the main module's principle of work, proposed one kind of new integral phase demodulation synchronized clock withdrew realizes the method, this method could enhance synchronized clock's accuracy, thus increased the error code measuring accuracy. Key word: Code error tester; FPGA; Discriminator; Digital phase-locked loop Introduction 　　The error code meter is appraises the channel performance the preliminary survey ...