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MAXQ3120 composite signal micro controller’s application case
Sunday, November 30th, 2008 at 15:12 | No commentsCategories: SCMShort Content: Supervisory system's designer and the manufacturer has hoped the micro controller can provide the general function which for the daily surveillance application increases unceasingly, including uses electricity satisfiedly aspect and so on measurement, automobile monitoring, data gathering and sensor adjustment requests. maxq3120 is to satisfy the low power loss which, the high speed micro controller these requests develop. Its major technique standard is as follows. •16, each second 8 1,000,000 instruction (8mips), monocycle risk nucleus •32kb dodges saves (the flash ... -
Cooperates the processing promotion wireless subsystem performance using FPGA
Saturday, November 29th, 2008 at 19:55 | No commentsCategories: EDA/PLDShort Content: You may obviously enhance in the wireless system the signal processing function performance. How to enhance? The efficacious device is and profits at present using the FPGA structure flexibility from parallel processing FPGA in the construction embedded DSP module. Common in wireless application this kind of processing including the limited impulse response (FIR) filter, fast Fournier transformation (FFT), digital high and low frequency conversion and forward error correction (FEC). Xilinx? Virtex-4 and the Virtex-5 construction provides reaches 512 parallel ... -
Uses DSP, PLD and ASIC realizes multispeed filter design comparison - 51RD the Chinese electronic net
Friday, November 28th, 2008 at 23:55 | No commentsCategories: EDA/PLDShort Content: Many communications systems must use the multispeed filter (multirate filter), the multispeed filter are refer to the output data speed and the data-in speed not equal filter, commonly used Yu physical interface like d/a converter (DAC) or modulus switch (ADC) connection place. When filter output data to DAC, user regular session choice interpolation filter, because it can produce more sampling points to cause DAC the output wave shape to be smoother; But when filter from ADC received signal, the user ... -
The G.726 pronunciation codec encoder-decoder realizes - en.51rd.net in SoPC
Friday, November 28th, 2008 at 18:55 | No commentsCategories: EDA/PLDShort Content: G.726 was ITU predecessor CCITT proposes in 1990 in G.721 and in the G.723 standard foundation about 64kbps the misalignment PCM signal conversion is 40kbps, 32kbps, 24kbps, the 16kbps ADPCM signal standard. The G.726 canonical algorithm is simple, the pronunciation quality is high, transforms after many times, the pronunciation quality has the guarantee, can achieve the network rank in the low bit rate the voice quality, thus obtained the widespread application in the pronunciation memory and the speech transmission domain. ... -
Realizes the video frequency and the image process application design using FPGA
Friday, November 28th, 2008 at 13:55 | No commentsCategories: EDA/PLDShort Content: Many beckoning technological innovations (for example HDTV and the digital theater) is and the video frequency and the image process technology as well as this kind of technical fast development cannot separate. The phantom capture and the demonstration resolution's caper type development, the advanced compress technique and the video frequency intelligence are precisely behind this kind of technological innovation the driving influence continuously. Specially the resolution in the past several years had the remarkable enhancement. Table 1 had demonstrated in ... -
Realizes the audio frequency sampling rate transformation with FPGA
Friday, November 28th, 2008 at 08:55 | No commentsCategories: EDA/PLDShort Content: Now, even if low cost FPGA can also provide is bigger than DSP by far the computing power. Present FPGA contains the special-purpose multiplier even DSP multiplication/to accumulate the (MAC) module, can by the 550MHz above clock speed processing signal. However, until now, in tonic train signaling processing also very little needs to use these functions. Serial realizes the kilohertz level audio frequency algorithm use resources to need with several hundred megacycle level signal processing identical. ... -
Based on FPGA and RTOS embedded symbol stream analysis design proposal
Thursday, November 27th, 2008 at 22:55 | No commentsCategories: EDA/PLDShort Content: Is expensive in view of the tradition digital video broadcast system symbol stream analyzer price, the use not convenient question, this article proposed that one kind of performance-to-price ratio good supplement design proposal, it take general FPGA and RTOS as the foundation, realizes the symbol stream analysis function based on the embedded hardware platform. In the article also elaborated symbol stream gathering, the symbol stream analysis and the information demonstration and so on many key technologies. The symbol stream ... -
In view of power design SDR solution
Thursday, November 27th, 2008 at 07:55 | No commentsCategories: EDA/PLDShort Content: Because looks like American union tactic radio system (JTRS) such plan, software definition's radio (SDR) was already confirmed. However, many questions are restricting the SDR widespread deployment seriously, the quite important question is a power. The power is in designs time each SDR subsystem's main consideration factor, because specially they must consume the hardware are radio than more powers. For example, to obtain the anticipated radio traffic to be away from (relies on link condition, typical value is ... -
DSP FPGA in high speed high fine movement controller’s application
Thursday, November 27th, 2008 at 02:55 | No commentsCategories: EDA/PLDShort Content: The movement control card already in the numerically-controlled machine tool, the industry robot, the medical equipment, the plotting machine, IC electric circuit domains and so on manufacture equipment, IC seal obtained the widespread utilization, has made the good progress. At present the movement control card uses 8051 series 8 monolithic integrated circuits majority, although saved the development cycle but to lack the flexibility, was competent the high request operation environment with difficulty, moreover the operational capability was limited. The ... -
Realizes the video frequency supervisory system’s video processing using FPGA
Wednesday, November 26th, 2008 at 21:55 | No commentsCategories: EDA/PLDShort Content: The video frequency supervisory system in the train station, the airport, the bank, the recreation area, the market family's security aspect is even one kind of key equipment. Along with security risk's day-by-day enlargement, to has sent the event in each kind of application situation to carry on the video frequency monitoring and the record demand gradually is rising, this request video frequency supervisory system's new structure must have the extendibility, in order to the diverse video frequency monitoring demand ...
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