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Asynchronous FIFO VHDL design_VHDL, fifo
Sunday, January 10th, 2010 at 04:53 | No commentsCategories: EDA/PLDShort Content: FIFO (advanced leaves formation is first) one kind obtains the widespread application component in the electronic system, usually uses in the data the buffer and uses in holding the asynchronous signal the frequency or the phase difference. FIFO realizes usually is use pair of mouth RAM and the read-write address has the module to realize. The FIFO connection signal including asynchronous writes the clock (wr_clk) and reads the clock (rd_clk), with to write the clock synchronization to write ... -
Based on TMS320C6000 DSP FIFO-network data transmission_DSP, fifo, TMS320C6000
Monday, December 7th, 2009 at 18:11 | No commentsCategories: Embedded systemShort Content: The networking in the rapid development, network interface's performance unceasingly is also enhancing. Because the ethernet connection cost is low, the speed is quick, the performance is good, the development is convenient, more and more data acquisition system uses the ethernet connection to take the final data output and the control port. But in corresponding embedded system domain, more and more chips, from monolithic integrated circuit to DSP, also gradually starts to support the ethernet connection. The TCP/IP ... -
Monolithic integrated circuit and FIFO connection assembly program_microcontroller, fifo
Monday, November 2nd, 2009 at 07:41 | No commentsCategories: Embedded systemTags: FIFO, microcontrollerShort Content: In the following procedure, after monolithic integrated circuit's reads FIFO in data, transmits from the serial port. ; *********************************** ef bit p3.3 ; fifo empty flag rst bit p3.5 ; reset fifo read bit p3.7 ; read fifo org 0000h ljmp main org 0030h main: ; ------ initial timer mov tmod,#00100001b ; timer0 mode 1 (16 bit) ; timer1 mode ... -
FPGA medium-soft FIFO designs and realizes - en.51rd.net
Monday, November 24th, 2008 at 14:55 | No commentsCategories: EDA/PLDShort Content: Abstract: In the modern circuit design, a system has often contained many clocks, how to transmit the data in the asynchronous clock between to become a very important question, but uses asynchronous FIFO to be possible to solve this problem effectively. Asynchronous FIFO was one kind obtains the widespread application component in the electronic system, in the article introduced one kind based on the FPGA asynchronous FIFO design method. Uses this method to be possible to design high speed, high ... -
Based on SRAM and DRAM structure large capacity FIFO design
Tuesday, November 4th, 2008 at 10:49 | No commentsCategories: StorageShort Content: Abstract: Separately based on Hynix Corporation's SRAM HY64UDl6322A and DRAM HY57V281620E, introduced uses two kind of different RAM structures, designs and realizes the large capacity FIFO method through CPLD.Key word: SRAM; DRAM; CPLD; Large capacity FIFO 1 introduction FIFO (First In First Out) is one kind has advanced leaves the memory function the first part, usually serves as the data buffer in the middle of the high speed figure system. In high speed data gathering, the transmission and in the ... -
Is suitable in the image detection compression system’s memory access mode
Saturday, October 18th, 2008 at 20:57 | No commentsCategories: StorageShort Content: In order to have both the extendibility and the data processing speed, regarding each kind of application, like the image data detects, the video data compression, the voice data to increase, the motor control wrong and so on, the programmable data processing module (Programmable Data Processing Module) is the current situation needs. In the processing data quantity bigger and bigger situation, the memory capacity which needs increases along with it, former advanced leaves the formation first (First-In-First-Out, FIFO) is ... -
Realizes asynchronous FIFO using FPGA design - 51RD the Chinese electronic net
Monday, August 18th, 2008 at 04:46 | No commentsCategories: EDA/PLDShort Content: At present the data acquisition system develops toward high speed and the high accuracy direction. Along with the FPGA integration rate and running rate's enhancement, may meet the high speed data gathering system's need. The FPGA interior has the rich memory cell, easy to realize each kind of memory (for example FIFO, pair of mouth RAM and so on); Moreover, may use in based on the search table's logical unit realizing each kind of digital signal processing (for example ...
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