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    • Based on Verilog HDL FIR digit filter design and simulation

      Tuesday, September 23rd, 2008 at 05:10 | No comments
      Categories: EDA/PLD
      Short Content: Abstract: This article has mainly analyzed the FIR digit filter's basic structure and the hardware constitution characteristic, introduced briefly the FIR filter realize way good and bad points; Unifies Altera Corporation's Stratix serial products characteristic, take one based on the MAC 8 step FIR digit filter's design as the example, gave has used the Verilog hardware description language to carry on the digital logic design the process and the method, and compiled the HDL code under the QuartusII integrated development ...
    • Based on Matlab TMS320LF2407 procedure fast design

      Monday, August 25th, 2008 at 14:23 | No comments
      Categories: DSP
      Short Content: The abstract under the Matlab/Simulink environment, designs the DSP procedure with the presente in figures and diagrams way, but reduced program design. Using Embedded Targetfor T1 C2000 the DSP tool bag, designs DSP the ADC conversion routine; Using the Simulink digital signal processing tool bag, designs the FIR filter clamour to carry on filter processing; Gives when the revision production C language procedure how to enable DSP to move correctly. The design procedure moves correctly on the TM$320LF2407A processor.Key word ...
    • Based on DSP C54x digital filter design

      Sunday, August 24th, 2008 at 01:43 | No comments
      Categories: DSP
      Short Content: Abstract: This article main introduction based on the DSP digital filter's design, uses CCS5000Simulator to realize the FTSK data feeds, uses the FIR filter to carry on processing for the FTSK modulation signal, the profile which and the frequency spectrum the output needs. In the article uses the linear buffer and the belt shifts the double operation addressing the method to realize the FIR filter.Key word: Digital filter, Matlab, Simulator Foreword     In an actual application system, always has each ...
    • FPGA realizes FIR algorithm in automobile dynamic weighing meter’s application

      Friday, August 22nd, 2008 at 06:56 | No comments
      Categories: EDA/PLD
      Short Content: Abstract: This article introduced realizes the FIR algorithm with FPGA, and applied to this algorithm in the automobile dynamic weighing measuring appliance's result has made the analysis. The practice proved that this algorithm uses in the dynamic weighing having the good effect.Key word: FPGA; FIR; Dynamic weighingIntroduction    Vehicles when dynamic weighing, affects in the platform the strength besides the real axis of reals heavy, but also many factors produce perturbed force, for example: The vehicle speed, vehicles own resonance, the ...
    • Different exponent number’s FIR digital filter’s DSP realizes - en.51rd.net

      Wednesday, August 20th, 2008 at 06:03 | No comments
      Categories: DSP
      Short Content:     The FIR filter's structure main right and wrong recursive structure, has not output the input the feedback. And the FIR filter are very easy to obtain the strict linear phase characteristic, avoids processing the signal to produce the phase distortion. But the linear phase manifests in the time domain is merely h (n) in the time detention, this characteristic in profile transmission systems and so on image signal processing, data transmission is very important. In addition, he will not ...
    • Based on XC2V1000 FPGA FIR extraction filter’s design

      Tuesday, August 19th, 2008 at 00:46 | No comments
      Categories: EDA/PLD
      Short Content: Abstract: Introduced that XC2V1000 scene programmable gate array (FPGA) principal characteristic and FIR extraction filter's principle of work, the key elaboration realizes the FIR extraction filter's method with XC2V1000, and gives the simulation profile and the design feature. Key word: FIR extraction filter; Stream line operation; XC2V1000; Scene programmable gate array 1 introduction    Extracts the filter widespread application in the digital receive domain, is under the digit frequency changer's hard core. At present, extracts the filter to realize ...
    Posts Tagged ‘FIR’

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