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Based on CPLD USB downloading electric cable design
Sunday, November 30th, 2008 at 00:55 | No commentsCategories: EDA/PLDShort Content: How does the abstract discuss designs, manufactures one kind to plant electric cable - - USB-blaster under the low cost usB data which QHattusII under the programer environment uses. According to the IEEEll49.1 standard, the USB agreement as well as the JTAG boundary scan principle, through analyzes the QuartusII internal communication mechanism, uses the USB chip and the CPLD union, proposed that one kind of USB interface circuit design with realizes the method. With traditional and the mouth, the serial ... -
Cooperates the processing promotion wireless subsystem performance using FPGA
Saturday, November 29th, 2008 at 19:55 | No commentsCategories: EDA/PLDShort Content: You may obviously enhance in the wireless system the signal processing function performance. How to enhance? The efficacious device is and profits at present using the FPGA structure flexibility from parallel processing FPGA in the construction embedded DSP module. Common in wireless application this kind of processing including the limited impulse response (FIR) filter, fast Fournier transformation (FFT), digital high and low frequency conversion and forward error correction (FEC). Xilinx? Virtex-4 and the Virtex-5 construction provides reaches 512 parallel ... -
Based on Nios II essence SOPC development board design
Saturday, November 29th, 2008 at 09:55 | No commentsCategories: EDA/PLDShort Content: Along with the EDA technology and microelectronic technology's swift development, the scene programmable gate array (Field Programmable Gate Array, was called FPGA) the performance has the large scale enhancement, the FPGA design level has also achieved a new altitude. The traditional embedded system design method has not been able to meet the current design need. Has brought a bigger flexibility based on the FPGA embedded system design for the modern electronic products design, develops the Nios II soft nuclear processor ... -
The G.726 pronunciation codec encoder-decoder realizes - en.51rd.net in SoPC
Friday, November 28th, 2008 at 18:55 | No commentsCategories: EDA/PLDShort Content: G.726 was ITU predecessor CCITT proposes in 1990 in G.721 and in the G.723 standard foundation about 64kbps the misalignment PCM signal conversion is 40kbps, 32kbps, 24kbps, the 16kbps ADPCM signal standard. The G.726 canonical algorithm is simple, the pronunciation quality is high, transforms after many times, the pronunciation quality has the guarantee, can achieve the network rank in the low bit rate the voice quality, thus obtained the widespread application in the pronunciation memory and the speech transmission domain. ... -
Realizes the video frequency and the image process application design using FPGA
Friday, November 28th, 2008 at 13:55 | No commentsCategories: EDA/PLDShort Content: Many beckoning technological innovations (for example HDTV and the digital theater) is and the video frequency and the image process technology as well as this kind of technical fast development cannot separate. The phantom capture and the demonstration resolution's caper type development, the advanced compress technique and the video frequency intelligence are precisely behind this kind of technological innovation the driving influence continuously. Specially the resolution in the past several years had the remarkable enhancement. Table 1 had demonstrated in ... -
Realizes the audio frequency sampling rate transformation with FPGA
Friday, November 28th, 2008 at 08:55 | No commentsCategories: EDA/PLDShort Content: Now, even if low cost FPGA can also provide is bigger than DSP by far the computing power. Present FPGA contains the special-purpose multiplier even DSP multiplication/to accumulate the (MAC) module, can by the 550MHz above clock speed processing signal. However, until now, in tonic train signaling processing also very little needs to use these functions. Serial realizes the kilohertz level audio frequency algorithm use resources to need with several hundred megacycle level signal processing identical. ... -
Realizes the multi-channel PWM output connection design and the simulation with FPGA
Friday, November 28th, 2008 at 03:55 | No commentsCategories: EDA/PLDShort Content: 0 introductions In many embedded system's practical applications, needs to expand FP-GA (the scene programmable gate array) the module, realizes CPU has the difficulty or realizes the efficiency low part to realize with FPGA, like the digital signal processing, the hardware digit filter, each algorithm and so on, or expand the I/O connection using FPGA, like realizes multi-channel PWM (pulse-duration modulation) to output, to realize the PCI connection expansion and so on. Through the reasonable system software and hardware function ... -
Based on FPGA and RTOS embedded symbol stream analysis design proposal
Thursday, November 27th, 2008 at 22:55 | No commentsCategories: EDA/PLDShort Content: Is expensive in view of the tradition digital video broadcast system symbol stream analyzer price, the use not convenient question, this article proposed that one kind of performance-to-price ratio good supplement design proposal, it take general FPGA and RTOS as the foundation, realizes the symbol stream analysis function based on the embedded hardware platform. In the article also elaborated symbol stream gathering, the symbol stream analysis and the information demonstration and so on many key technologies. The symbol stream ... -
Based on CPLD MIDI music player design
Thursday, November 27th, 2008 at 17:55 | No commentsCategories: EDA/PLDShort Content: Abstract: This music player rests on the MIDI music basic principle, unifies the EDA technology, uses the ALTERA Corporation's programmable logical component (CPLD) EPF10LC84-4 to design as the control core. This article mainly elaborated uses VHDL the language design MIDI music generator chip, is joined to the essential peripheral circuit again, thus realizes four music choice broadcast, and has along with music rhythm glitters change function and so on colored lantern EDA application systems. Key words: EDA, CPLD, music ... -
In video frequency supervisory system based on FPGA video processing
Thursday, November 27th, 2008 at 12:55 | No commentsCategories: EDA/PLDTags: FPGA, The video frequency monitorsShort Content: The video frequency supervisory system is the train station, the airport, the bank, the recreation area, the shopping center even family security's important module. Increases along with the security risk, increases sharply to the visual surveillance and the record event's demand by many kinds of use patterns. Therefore, the new construction must the numerous and diverse video frequency supervisory system request cost benefit plan provide the extendibility day after day for the spread-eagle one whole set. The going on ...
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