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Thursday, August 21st, 2008 at 20:56 | No comments

Categories: EDA/PLD

Tags: automated proof system, e language, HDL language

Short Content: Proof technique development    In the present integrated circuit design, the chip scale and the complex degree are assuming the index to increase, designs the chip function for the guarantee the accuracy, needed to spend compared to formerly more time and the manpower, the degree of difficulty increases largely. Moreover, present function confirmation ability already by far fell behind the designed capacity, the function confirmation is becoming the large-scale chip design the bottleneck. The designers usually need to spend 50%~70% time ...