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Tuesday, November 25th, 2008 at 15:55 | No comments

Categories: EDA/PLD

Tags: FPGA, IP nucleus, SoC, uart

Short Content: Abstract: This article has designed one kind based on the FPGA UART nucleus, this nucleus conforms to the serial communication agreement, has the modulation, the compatibility and configurable, suits applies in SoC. In the design uses Verilog the HDL hardware description language environment to carry on the design, the simulation in Xilinx under the ISE, finally inserted UART on FPGA the IP nucleus to realize electric circuit's asynchronous serial communication function.  Key word: IP nucleus; UART; Verilog HDL; FPGA  ...

Monday, November 24th, 2008 at 14:55 | No comments

Categories: EDA/PLD

Tags: connection, FIFO, FPGA, IP nucleus

Short Content: Abstract: In the modern circuit design, a system has often contained many clocks, how to transmit the data in the asynchronous clock between to become a very important question, but uses asynchronous FIFO to be possible to solve this problem effectively. Asynchronous FIFO was one kind obtains the widespread application component in the electronic system, in the article introduced one kind based on the FPGA asynchronous FIFO design method. Uses this method to be possible to design high speed, high ...

Wednesday, November 19th, 2008 at 20:12 | No comments

Categories: EDA/PLD

Tags: FPGA, IP nucleus, MVB, SOPC

Short Content: Abstract brief introduction tradition MVB communication controller chip MVBC structure and function; Through the deep research MVB first floor communication protocol, designs conforms to the IEC-61375 standard to use in the network connections the MVB main line visiting IP (Intellectual Property) the nucleus; Based on SOPC design concept. Integrated 32 NiosII soft nuclear processors and the MVB main line using SOPC Builder on piece of FPGA visits the IP nucleus, as well as some essential periphery module, and gives the ...

Sunday, November 16th, 2008 at 17:12 | No comments

Categories: EDA/PLD

Tags: FPGA, IP nucleus, SoC, uart

Short Content: Abstract: This article has designed one kind based on the FPGA UART nucleus, this nucleus conforms to the serial communication agreement, has the modulation, the compatibility and configurable, suits applies in SoC. In the design uses Verilog the HDL hardware description language environment to carry on the design, the simulation in Xilinx under the ISE, finally inserted UART on FPGA the IP nucleus to realize electric circuit's asynchronous serial communication function.  Key word: IP nucleus; UART; Verilog HDL; FPGA  ...

Thursday, September 25th, 2008 at 22:10 | No comments

Categories: EDA/PLD

Tags: FPGA, IP nucleus, RS encoder

Short Content: Abstract: Designed one kind of code length to variable, error correction ability adjustable RS encoder. This RS encoder may carry on the code to the commonly used RS cut number, may make the IP nucleus, has provided very big convenient for the user; Uses based on multiplication of polynomials theory GF (2m) on m fast galois field multiplication method, raised encode circuit's operating speed; Simultaneously has given the procedure simulation result, and has carried on the hardware confirmation on Xilinx ...

Thursday, September 18th, 2008 at 05:09 | No comments

Categories: EDA/PLD

Tags: 8051, FPGA, IP nucleus, tcp/ip

Short Content: Introduction Is getting bigger and bigger along with the chip scale, the resources to be getting more and more rich, the chip design order of complexity also greatly increases. In fact, after the chip design completes, sometimes also needs according to conversion some controls, this in the use process frequently to meet. At this time if will carry on the change to the chip design will be again very may not take, because will need the designers to participate in ...

Thursday, August 21st, 2008 at 00:56 | No comments

Categories: EDA/PLD

Tags: C2H the tool, IP nucleus, knowledge reads, SOPC, voice print characteristic

Short Content: Picking   Wanting: In nowadays's electronic products development domain, holds the extremely important status based on FPGA SOPC. This article introduced based on SOPC, the inserting biological features' individual credential knowledge reads the design. And, the biological features mainly take the voice print characteristic as a goal, inserts it to the two-dimensional bar code, prints the bar code again to individual credential, uses in individual credential the forgery-proof confirmation. This design uses Altera Corporation's FPGA soft nuclear processor as well as ...