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Sunday, August 17th, 2008 at 23:46 | No comments

Categories: EDA/PLD

Tags: data minute meets, DDS, FPGA, m sequence, The data multiple connection

Short Content: Abstract: This article used FPGA to complete 8 group synchronized voices and 16 group asynchronous data multiple connection meets the process with the minute, and before having realized multiple connection's frame synchronization capture and carries on the frequency division using DDS to the clock source to obtain needs clock's process. This design's control module completes by the VHDL language, finally tool and the Modelsim tool has completed this design behavior simulation, the layout wiring simulation and the succession simulation using ...