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    • Based on RVM hierarchical SoC chip platform design and application

      Tuesday, September 23rd, 2008 at 10:10 | No comments
      Categories: EDA/PLD
      Short Content: Is day by day complex along with the SoC design, confirms into the SoC design process the most essential link. This article introduced the Synopsys RVM confirmation methodology, uses the Vera hardware confirmation tool as well as the OpenVera confirmation language establishment simulated target environment, produces the drive automatically, completes from work and so on checkup test, coverage fraction analysis. Confirms the platform through the establishment hierarchization's reusability, enhanced greatly has confirmed engineer's working efficiency. In the article take a ...
    Posts Tagged ‘RVM confirmation’

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