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Nucleus design with realizes - en.51rd.net based on FPGA UART the IP
Tuesday, November 25th, 2008 at 15:55 | No commentsCategories: EDA/PLDShort Content: Abstract: This article has designed one kind based on the FPGA UART nucleus, this nucleus conforms to the serial communication agreement, has the modulation, the compatibility and configurable, suits applies in SoC. In the design uses Verilog the HDL hardware description language environment to carry on the design, the simulation in Xilinx under the ISE, finally inserted UART on FPGA the IP nucleus to realize electric circuit's asynchronous serial communication function. Key word: IP nucleus; UART; Verilog HDL; FPGA ... -
Accelerates ASIC/SoC the prototype project software technique - 51RD the Chinese electronic net
Friday, November 21st, 2008 at 22:12 | No commentsCategories: EDA/PLDShort Content: ASIC and the SoC component cost's gradual rise force semiconductor supplier must further develop each component's market to seek satisfaction the investment repayment. Day by day the growth software use has provided the effective mechanism for this reason, because increases the software content equated in more functions and the software change has provided the particular market product variation. This tendency caused over a million line of software codes appears in ASIC or SoC is also nothing unusual. The multi-essence's use ... -
Nucleus design with realizes - en.51rd.net based on FPGA UART the IP
Sunday, November 16th, 2008 at 17:12 | No commentsCategories: EDA/PLDShort Content: Abstract: This article has designed one kind based on the FPGA UART nucleus, this nucleus conforms to the serial communication agreement, has the modulation, the compatibility and configurable, suits applies in SoC. In the design uses Verilog the HDL hardware description language environment to carry on the design, the simulation in Xilinx under the ISE, finally inserted UART on FPGA the IP nucleus to realize electric circuit's asynchronous serial communication function. Key word: IP nucleus; UART; Verilog HDL; FPGA ... -
Uses the new SRAM craft to realize embedded ASIC and the SoC memory design
Tuesday, November 11th, 2008 at 07:49 | No commentsCategories: StorageShort Content: The sharp weapon which has been in many embedded designs uses ASIC/SoC based on the traditional six transistor (6T) memory cell's static RAM memory block to realize the development personnel who uses, because of this kind of memory structure very suitable mainstream's CMOS technical process, not to need to increase any extra craft step. Like in chart 1a shows such, interwove basically the coupling latch and the active load unit has composed the 6T memory cell, this kind of ... -
Based on C8051F320 USB connection data acquisition storage circuit
Saturday, October 18th, 2008 at 00:57 | No commentsCategories: StorageShort Content: Abstract: The introduction uses C8051F320 SOC and the AM45DB321 constitution data acquisition memory system's design proposal.Key word: Data acquisition; USB connection; Storage circuit; SOC Sometimes in some special industry situation, needs and saves sensor's signal unceasing real-time gathering, and playbacks again to certain time the data to PC machine in carries on the analysis and processing. Used the high performance perhaps in the working conditions bad situation the monolithic integrated circuit and the technical grade large capacity FLASH memory's plan ... -
Based on RVM hierarchical SoC chip platform design and application
Tuesday, September 23rd, 2008 at 10:10 | No commentsCategories: EDA/PLDTags: RVM confirmation, SoCShort Content: Is day by day complex along with the SoC design, confirms into the SoC design process the most essential link. This article introduced the Synopsys RVM confirmation methodology, uses the Vera hardware confirmation tool as well as the OpenVera confirmation language establishment simulated target environment, produces the drive automatically, completes from work and so on checkup test, coverage fraction analysis. Confirms the platform through the establishment hierarchization's reusability, enhanced greatly has confirmed engineer's working efficiency. In the article take a ... -
Confirms the platform design and the application based on the RVM hierarchical SoC chip
Wednesday, September 17th, 2008 at 19:09 | No commentsCategories: EDA/PLDShort Content: Abstract: This article take the SIM card control module's function confirmation as an example, introduced confirmation tool as well as the RVM confirmation methodology builds the high grade confirmation platform highly effective fast using Synopsys the Vera the method. In the article introduced in detail the RVM confirmation methodology as well as RVM confirm the platform the structure.Key word: RVM; SoC; Confirms the platform; Reusability; Function confirmationIntroductionIs day by day complex along with the SoC design, confirms into the SoC ... -
Based on SoC AC’97 technology hardware design
Sunday, August 24th, 2008 at 13:56 | No commentsCategories: EDA/PLDShort Content: Introduction Conforms to Audio the Codec'97 agreement (i.e. AC'97, is digital audio frequency processing agreement which proposed by Intel Corporation) not only the audio frequency controller widely applies in the personal computing sound card, and (for example Intel PXA250) provides the audio frequency solution for individual information terminal device's SOC. This article designs the audio frequency controller may be the DSP essence provides the digital audio frequency connection. The full text during introduction audio frequency controller structure's, stressed emphatically it with ... -
But multiplying SPI module IP nucleus design and confirmation
Saturday, August 9th, 2008 at 17:06 | No commentsCategories: EDA/PLDTags: SoCShort Content: Abstract: SoC is the ultra large scale integrated circuit's trend of development and the new century integrated circuit's mainstream. Its complexity as well as cost fast requests and so on completes the design, to reduce, had decided system-on-a-chip's design must use IP (Intellectual Property) the multiplying method. This article introduced that by may the multiplying IP design method, design serial peripheral device connection SPI (Serial Peripheral Interface) the module IP nucleus mentality, realize with the Verilog language, and after ...
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