-
Based on Nios II essence SOPC development board design
Saturday, November 29th, 2008 at 09:55 | No commentsCategories: EDA/PLDShort Content: Along with the EDA technology and microelectronic technology's swift development, the scene programmable gate array (Field Programmable Gate Array, was called FPGA) the performance has the large scale enhancement, the FPGA design level has also achieved a new altitude. The traditional embedded system design method has not been able to meet the current design need. Has brought a bigger flexibility based on the FPGA embedded system design for the modern electronic products design, develops the Nios II soft nuclear processor ... -
The G.726 pronunciation codec encoder-decoder realizes - en.51rd.net in SoPC
Friday, November 28th, 2008 at 18:55 | No commentsCategories: EDA/PLDShort Content: G.726 was ITU predecessor CCITT proposes in 1990 in G.721 and in the G.723 standard foundation about 64kbps the misalignment PCM signal conversion is 40kbps, 32kbps, 24kbps, the 16kbps ADPCM signal standard. The G.726 canonical algorithm is simple, the pronunciation quality is high, transforms after many times, the pronunciation quality has the guarantee, can achieve the network rank in the low bit rate the voice quality, thus obtained the widespread application in the pronunciation memory and the speech transmission domain. ... -
Realizes the multi-channel PWM output connection design and the simulation with FPGA
Friday, November 28th, 2008 at 03:55 | No commentsCategories: EDA/PLDShort Content: 0 introductions In many embedded system's practical applications, needs to expand FP-GA (the scene programmable gate array) the module, realizes CPU has the difficulty or realizes the efficiency low part to realize with FPGA, like the digital signal processing, the hardware digit filter, each algorithm and so on, or expand the I/O connection using FPGA, like realizes multi-channel PWM (pulse-duration modulation) to output, to realize the PCI connection expansion and so on. Through the reasonable system software and hardware function ... -
Based on FPGA and RTOS embedded symbol stream analysis design proposal
Thursday, November 27th, 2008 at 22:55 | No commentsCategories: EDA/PLDShort Content: Is expensive in view of the tradition digital video broadcast system symbol stream analyzer price, the use not convenient question, this article proposed that one kind of performance-to-price ratio good supplement design proposal, it take general FPGA and RTOS as the foundation, realizes the symbol stream analysis function based on the embedded hardware platform. In the article also elaborated symbol stream gathering, the symbol stream analysis and the information demonstration and so on many key technologies. The symbol stream ... -
In view of power design SDR solution
Thursday, November 27th, 2008 at 07:55 | No commentsCategories: EDA/PLDShort Content: Because looks like American union tactic radio system (JTRS) such plan, software definition's radio (SDR) was already confirmed. However, many questions are restricting the SDR widespread deployment seriously, the quite important question is a power. The power is in designs time each SDR subsystem's main consideration factor, because specially they must consume the hardware are radio than more powers. For example, to obtain the anticipated radio traffic to be away from (relies on link condition, typical value is ... -
Uses the new SRAM craft to realize embedded ASIC and the SoC memory design
Tuesday, November 11th, 2008 at 07:49 | No commentsCategories: StorageShort Content: The sharp weapon which has been in many embedded designs uses ASIC/SoC based on the traditional six transistor (6T) memory cell's static RAM memory block to realize the development personnel who uses, because of this kind of memory structure very suitable mainstream's CMOS technical process, not to need to increase any extra craft step. Like in chart 1a shows such, interwove basically the coupling latch and the active load unit has composed the 6T memory cell, this kind of ... -
Links USB to dodge saves the plate and PIC the micro controller’s simple plan
Tuesday, November 11th, 2008 at 02:49 | No commentsCategories: StorageShort Content: This article introduced that uses the low cost PIC micro controller to connect USB through the USB2.0 full speed bridge chip to dodge saves of design method the plate, it focuses on the PIC micro controller and VNC1L intelligence USB the Host bridge chip the embedded connection hardware design, as well as explained how to carry on the procedure development in the PIC micro controller, causes the universal existence USB to dodge saves the plate to be able to take ... -
In embedded system design memory fragment collection strategy - 51RD Chinese electronic net
Sunday, November 9th, 2008 at 00:49 | No commentsCategories: StorageShort Content: Along with embedded system data object process load's sharp growth, to saves the fragment collection the real-time performance request also appears day by day prominent, this article will introduce truely highly effective, real-time, the definite two kind of memory fragment collection technology engineer to provide in the strategy to (China) the instruction. In the embedded system design process, which data Java didn't the programmer need to clarify to take which memories or should release which storage space in any ...
51 Research and Design, Electronic Engineers website - Embedded Systems, MCU, DSP, EDA, Test and Measurement, Components, Communications, Power, Microelectronics, Semiconductors
Electronic Design and Research - Electronic Engineers website
