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The N odd number frequency division method summarizes_Verilog, sub-frequency, odd-numbered
Tuesday, January 12th, 2010 at 22:08 | No commentsCategories: EDA/PLDShort Content: The N odd number frequency division, must make the dutyfactor is 50%, realizes by the following mentality:A, by an original clock cycle N time of achievement processing period; (function which counts with counter)B, the production dutyfactor is N2: N2 1 (division takes entire) profile; (by counter value sampling)C, B production profile phase-shift original clock's a half cycle; (with negative along function which hits)D, if the high level occupies the N2 width, outputs B and the C profile or; If the ... -
Verilog discussion group splendid content extract_Verilog
Tuesday, January 12th, 2010 at 01:33 | No commentsCategories: EDA/PLDTags: VerilogShort Content: Question: I have met a question, hoped that can obtain the help. I when use FPGA (ALTERA 10K30) does the simulation experiment, the internal counter counting is not always normal, but I in the microcomputer with the ModelSim simulation's result am correct, therefore logic should not have the question, the question leaves in FPGA, consults everybody, how should I solve this problem. Thanks! I met a question, hope someone could do me a favor. when I used FPGA do simulating experiment, i ... -
Verilog cryptoprinciple_Verilog, code
Monday, January 11th, 2010 at 16:52 | No commentsCategories: EDA/PLDShort Content: Rule #1: When establishment sequential logic model, uses the non-blocking assignment statement.Rule #2: When establishes the latch model, uses the non-blocking assignment statement.Rule #3: Establishes the combinatory logic model when the always block, uses the blocking assignment statement.Rule #4: Simultaneously has the combination and the sequential logic in a always block at times, uses the non-blocking assignment statement.Rule #5: Simultaneously do not use blocking and the non-blocking assignment statement in a always block.Rule #6: The identical variable do not ... -
In numerical calculus Bcd code checking circuit
Sunday, January 10th, 2010 at 22:27 | No commentsCategories: EDA/PLDShort Content: Abstract: In the computer numerical calculus, the value is frequently carries on the operation by the BCD code. Therefore the BCD checking circuit is a very important hardware logic. Not only its affects correctly the numerical calculus or not, but also has the decision function to the entire operation's speed. This article has first analyzed the BCD code verification principle, then from parallel, the serial two kind of circuit structure has analyzed the BCD code verification logic. Finally proposed ... -
A simple main line polling arbitration Verilog code_Verilog, the bus arbiter poll
Sunday, January 10th, 2010 at 17:30 | No commentsCategories: EDA/PLDTags: the bus arbiter poll, VerilogShort Content: Below this is takes state machine's jump condition by the input signal, writes quite redundant://// Verilog Module demo1_lib.bus_arbitor.arch_name//// Created:// by - Newhand// in - Shanghai ZhangJiang// at - 20:39: 41 2003-12-03// using Mentor Graphics HDL Designer(TM)/////////////////////////////////////////////////////////////// Discription:// Bus Polling Arbitor (BPA)on // main line hangs 3 signal A, B, C, arbitrates signal grant[1:0].// grant[1:0]=2'b00 A obtains the main line// grant[1:0]=2'b01 B obtains the main line// grant[1:0]=2'b10 C obtains the main lineif // main line polling algorithm a. current has ... -
State machine example_Verilog, state machine
Sunday, January 10th, 2010 at 08:48 | No commentsCategories: EDA/PLDTags: state machine, VerilogShort Content: You may assign the condition register and state machine's condition. The following is one has four condition ordinary state machines. // These are the symbolic names for states// definition state mark nameparameter [1:0] S0 = 2 ' h0, S1 = 2 ' h1, S2 = 2 ' h2, S3 = 2 ' h3; // These are the current state and next state variables// defines the current condition and the next state variablereg [1:0] state;reg [1:0] next_state; // state_vector ... -
verilog the HDL design practices to enter the step (one ) Verilog, practice _Verilog
Sunday, January 10th, 2010 at 01:59 | No commentsCategories: EDA/PLDTags: VerilogShort Content: Practices one. Simple combinatory logic design Goal: Grasps the basic combinatory logic electric circuit to realize the method. This is the data comparator which may synthesize, very easy to see its function is comparative data a and data b, if two data are the same, then gives the result 1, otherwise gives the result 0. In Verilog HDL, the description combinatory logic often uses the assign structure. Pays attention to equal=(a==b)? 1:0, this is one kind realizes ... -
Verilog the HDL design practices to enter the step (two ) Verilog, practice _Verilog
Sunday, January 10th, 2010 at 00:57 | No commentsCategories: EDA/PLDTags: VerilogShort Content: Practices two. Simple sequential logic electric circuit's design Goal: Grasps basic sequential logic electric circuit's realization. In Verilog HDL, is opposite in the combinatory logic electric circuit, the sequential logic electric circuit also has the stipulation indication way. In Verilog which may synthesize HDL model, we usually use the always block and @ (posedge clk) or @ (negedge clk) the structure indicates the sequential logic. Below is a 1/2 frequency divider may the unified model. // half_clk.v: ... -
Verilog the HDL design practices to enter the step (three ) Verilog, practice _Verilog
Saturday, January 9th, 2010 at 23:05 | No commentsCategories: EDA/PLDTags: VerilogShort Content: Practices three. Realizes the complex sequential logic electric circuit using the statement Goal: Grasps the statement in the Verilog HDL use. Is the same with the commonly used high level language, to describe the more complex succession relations, Verilog HDL has provided the statement for the branch judgment when uses. In may synthesize the style Verilog in the HDL model the commonly used statement to have if…else and the case…endcase two kind of structures, in usage and C ... -
Verilog the HDL design practices to enter the step (four ) Verilog, practice _Verilog
Saturday, January 9th, 2010 at 22:04 | No commentsCategories: EDA/PLDTags: VerilogShort Content: Practices four. When design sequential logic uses the blocking evaluation and the non-blocking evaluation difference Goal: 1. grasps the blocking evaluation and the non-blocking evaluation concept and the difference explicitly; 2. understanding blocking evaluation service condition. In the circuit structure difference which the blocking evaluation with the non-blocking evaluation, we had already understood between them in the teaching material after grammar difference as well as synthesis obtains. In the always block, the blocking evaluation may understand that ...
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