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Based on FPGA USB2.0 controller design
Friday, November 21st, 2008 at 12:12 | No commentsCategories: EDA/PLDShort Content: In the video frequency memory and in the image wide band domain, meets the real-time high speed data transmission frequently the request. in April, 2000, USB2.0 which by companies and so on Intel, Microsoft, NEC, Compaq, Lucent, Phillips drew up together (Universal Serial Bus) the transport protocols, its speed went far beyond present has used the IEEE1394 connection to carry on the video frequency transmission 400Mbps, has achieved 480Mbps; And has PnP which namely inserts namely uses (Plug And Play), ... -
Entire digital three prosperous thyratron trigger IP soft nucleus design - 51RD Chinese electronic net
Wednesday, November 19th, 2008 at 15:12 | No commentsCategories: EDA/PLDShort Content: IP (Intellectual Propcrty) is the intellectual property rights which often said. The American Dataquest Consultant firm defines semiconductor industry's IP to use in ASIC, ASSP and PLD in the middle and so on, and is the preliminary design good electric circuit module. The IP nuclear module has behavior (Behavior), structure (Structure) and the physical (Physical)_ three level of varying degree designs. According to the description function behavior's difference, the IP nucleus divides into three kinds. Namely the soft nucleus (Soft ... -
Uses VHDL language design FPGA several frequently asked questions discussions
Tuesday, October 28th, 2008 at 19:17 | No commentsCategories: EDA/PLDShort Content: Does wants: Discussed in detail in MAX plusⅡDevelops under the platform to use the VHDL hardware describes when language design scene programmable gate array (FP-GA) the common three questions: And so on dutyfactor frequency dividing circuits, time delay random quantity delay circuit, bilateral circuit.Key word: FPGA; VHDL; Frequency dividing circuit; Delay circuit; Bilateral circuit 1 introduction Along with the EDA technology's development, uses the hardware language to design programmable logical component (PLD)/scene programmable gate array (FPGA) to become one tendency. ... -
Based on scene programmable gate array numerical control delayer design
Tuesday, October 28th, 2008 at 04:17 | No commentsCategories: EDA/PLDShort Content: Abstract: Gives one kind based on the scene programmable gate array (FPGA) numerical control delayer design method. First introduced in detail the use counter the series realizes the controllable time delay method, then discusses under the different time delay scope this numerical control delayer improvement program, ultimate analysis time delay error and time delay precision. The delayer exterior connection imitates the AD9501 design.Key word: FPGA; VHDL; AD9501; Numerical control delayer; Radar target simulator l introduction Unifies programmable logical component (PLD) ... -
Microcomputer protection control interface installment CPLD antijamming design
Sunday, October 26th, 2008 at 12:17 | No commentsCategories: EDA/PLDShort Content: Abstract: Introduced that one kind designs the microcomputer protective system control interface with VHDL on the CPLD chip the method to enhance the resistance to interference, the test result indicated: Control interface's resistance to interference is very high, realizes the microcomputer protective system's redundant reliable control completely. The connection speed is high, the high integration rate, can direct and the high speed DSP system connection, has the high promoted value.Key word: Microcomputer protection; Antijamming; Redundancy design; VHDL; CPLD Directing Word The microcomputer protective ... -
The multi-specification S box’s hardware realizes the method
Saturday, October 18th, 2008 at 05:18 | No commentsCategories: Communication NetworksShort Content: IntroductionIn the information field, the crypto-algorithm uses in protecting the information the secrecy, the integrity and the security, puts briefly is prevents the information fabrication and steals. The crypto-algorithm may divide into the symmetrical crypto-algorithm and the asymmetrical crypto-algorithm. The symmetrical crypto-algorithm's characteristic is the speed quick, the working strength is high, mainly serves as the data encryption algorithm. The symmetrical crypto-algorithm may divide into the block cipher algorithm and the sequential cipher algorithm according to the encryption pattern. The ... -
FPGA and SRAM unify complete the large capacity data storage
Wednesday, October 15th, 2008 at 16:54 | No commentsCategories: StorageShort Content: 1 introduction Along with the digital signal processing technology's unceasing development, the large capacity programmable logical component's unceasing emergence, the FPGA technology more and more applies in the large scale integrated circuit design. In this hardware system design, will meet frequently needs the large capacity data storage the situation, below we will aim in FPGA internal Block the RAM limited shortcoming, proposed will unify FPGA with exterior SRAM improves the design the method, and has given the part VHDL ... -
Based on FPGA TDI-CCD sequence circuit’s design
Sunday, September 21st, 2008 at 23:10 | No commentsCategories: EDA/PLDShort Content: Abstract: In order to solve TDI-CCD to take the remote sensing camera's image sensor the sequence circuit design question which faces in the use, in the article introduced in detail the TDI-CCD structure and the principle of work, and the IL-E2 TDI-CCD characteristic which uses according to the engineering project, has designed one kind based on the scene programmable gate array (FPGA) TDI-CCD sequence circuit, its actuation succession use standard's hardware describes the language VHDL compilation, the succession simulation profile ... -
Based on CPLD PSK system design
Tuesday, September 16th, 2008 at 10:36 | No commentsCategories: EDA/PLDShort Content: Abstract: The present paper mainly discussed and the simulation based on the CPLD PSK system unit design, during elaboration modulation demodulation system's basic principle and design method, also introduced in detail system's overall electric circuit diagram and each module's concrete software and hardware realized. The author takes the design by VHDL the hardware description language, in Altera Corporation's Maxplus2 developed in the platform to carry on the programming and the profile simulation. is this design main characteristic "from the top", ... -
May expand the multi-channel multicast duplications based on the FPGA bit wide to realize - en.51rd.net
Thursday, September 11th, 2008 at 02:02 | No commentsCategories: EDA/PLDShort Content: Abstract: Realizes the multicast duplication with the VHDL language in the FPGA interior programming. This article introduced that it realizes the method, and has given the succession simulation profile. Through the expansion, this design may support the multi-bit wides, the multi-channel duplications, thus has the good application prospect.Key word: FPGA VHDL multicast duplication 1 outline The multicast is one data packet transmission mode, when has the receiver who many main engines simultaneously become a data packet, stemming from to ...
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