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VHDL in high speed image gathering system
Tuesday, January 12th, 2010 at 18:07 | No commentsCategories: EDA/PLDTags: image acquisition, VHDLShort Content: The modernized production and the scientific research enhance day by day to the image gathering system's request. The traditional image gathering card speed is slow, the processing function is simple, cannot satisfy the special request well, therefore, we have constructed the high speed image gathering system. It mainly includes the image gathering module, the image preliminary processing module as well as the bus interface module and so on. These modules are realize in FPGA using the VHDL programming. The ... -
In the VHDL design the electric circuit simplifies the question the discussion_VHDL, circuit simplification
Tuesday, January 12th, 2010 at 16:14 | No commentsCategories: EDA/PLDTags: circuit simplification, VHDLShort Content: In recent years, along with the integrated circuit technology's development, carried on the chip or the system design with the traditional method has not been able to satisfy the request, urgent needs to raise the rated capacity. Under such technical background, can reduce the design difficulty the VHDL design method more and more widely to use greatly. But the VHDL design is the behavior level design?? Brings the question is designer's design ponder and circuit structure comes apart. ... -
Enhances VHDL in the PLD development the comprehensive quality_VHDL, synthesis, PLD
Tuesday, January 12th, 2010 at 15:12 | No commentsCategories: EDA/PLDShort Content: Introduction Along with computer and microelectronic technology development, electronic design automation EDA (Electronic Design Automation) and programmable logical component PLD (Programmable Logic Device) the development is rapid, uses the EDA software to carry on PLD skilled the component development to become the basic skill which electronic engineer must grasp. The advanced EDA tool already from the traditional design method change from bottom to top for the design method from the top, (Hardware Description Language) described the system-level ... -
The VHDL design disappears shakes with the filter_VHDL, filtering, eliminate buffeting
Tuesday, January 12th, 2010 at 12:18 | No commentsCategories: EDA/PLDShort Content: With together circuit wafer on, because the holding wire the high frequency burr which walks the line to be excessively long produces we may through, in the close input end connects 100 ohm about the resistance to filter. But regarding the board outside the signal, or in the board other disturbances creates time the big vibration has to use the integrated circuit to come the filter, namely strings together a resistance also to want and a capacity ground. ... -
Frequency divider
Tuesday, January 12th, 2010 at 06:31 | No commentsCategories: EDA/PLDShort Content: In the digital circuit, often needs to carry on the frequency division operation to the high frequency clock, obtains compares the low frequency the clock signal. We knew, when hardware circuit design clock signal is important. Below we introduced that frequency divider's VHDL description, completes in the source code to the clock signal CLK 2 frequency divisions, 4 frequency divisions, 8 frequency divisions, 16 frequency divisions.LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY clkdiv IS PORT (clk : IN STD_LOGIC; ... -
VHDL stopwatch timer_VHDL, stopwatch timer
Tuesday, January 12th, 2010 at 05:29 | No commentsCategories: EDA/PLDTags: stopwatch timer, VHDLShort Content: This stopwatch timer uses in the sports competition and each kind of request have are precise when various domains. This timer is with a special-purpose chip, describes with the VHDL language. It besides the switch, the clock and the demonstration function, it also includes 1/100s timer all controls and fixed time the function, its volume is small, carries conveniently. Timer's design function: (1) the precision should be bigger than 1/100s (2) when timer's most long-range plan is 1 ... -
VHDL design example: A simple UART_UART, VHDL
Monday, January 11th, 2010 at 20:47 | No commentsCategories: EDA/PLDShort Content: -------------------------------------------------------------------- Copyright (c) 1992,1993,1994, Exemplar Logic Inc. All rights reserved.---------------------------------------------------------------------- This design implements a UART. ---- -- Version 1.1: Original Creation-- Version 1.2: Modified to std_logic types-- Version 2.1: Extended reset to be more effective.-- Introduced OTHERS clause.------------------------------------------------------------------ LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all; ENTITY uart IS PORT (clkx16: IN std_logic; -- Input clock. 16x bit clock read: IN std_logic; -- Received data read strobe write: IN std_logic; -- Transmit data write strobe rx: IN std_logic; -- Receive data line reset: IN ... -
VHDL design example: Pseudo-random numbers producer_VHDL, pseudo-random number
Monday, January 11th, 2010 at 19:45 | No commentsCategories: EDA/PLDTags: pseudo-random number, VHDLShort Content: ----------------------------------------------------------------------------- -- -- The following information has been generated by Exemplar Logic and -- may be freely distributed and modified. -- -- Design name: pseudorandom -- -- Purpose: This design is a pseudorandom number generator. This design -- will generate an 8-bit random number using the polynomial p(x) = x 1. -- This system has a seed generator and will generate 2 ** 8 - 1 unique -- vectors in pseudorandom order. These vectors are stored in ... -
Gray code counter design mentality_VHDL, Gray-code counter
Sunday, January 10th, 2010 at 21:27 | No commentsCategories: EDA/PLDTags: Gray-code counter, VHDLShort Content: We knew that the gray code counting the characteristic is the neighboring symbol only then a bit difference, then we in design gray code counting time found this bit to take instead and that's the end. Found this bit mentality: Converts the first gray code the binary code, in this binary code from LSB to MSB first is ' 0 ' the bit correspondence's gray code position namely for needs the position, if entire ' 1 ', then ... -
Introduces state machine
Sunday, January 10th, 2010 at 20:24 | No commentsCategories: EDA/PLDTags: state machine, VHDLShort Content: Borrows zqadam the logic to change:`define S1 0`define S2 1`define S3 2`define S4 3`define S5 4`define S6 5`define S7 6`define S8 7 module clk_gen2 (clk, reset, clk1, clk2, clk4, fetch, alu_clk); input clk, reset;output clk1, clk2, clk4, fetch, alu_clk; wire clk, reset;reg clk2, clk4, fetch, alu_clk;reg[7:0] state, next_state; wire s_s1 = state [`S1];wire s_s2 = state [`S2];wire s_s3 = state [`S3];wire s_s4 = state [`S4];wire s_s5 = state [`S5];wire s_s6 = state [`S6];wire s_s7 = state [`S7];wire s_s8 = ...
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