51 Research and Design, Electronic Engineers website - Embedded Systems, MCU, DSP, EDA, Test and Measurement, Components, Communications, Power, Microelectronics, Semiconductors

Sunday, September 7th, 2008 at 08:02 | No comments

Categories: EDA/PLD

Tags: clock recovery, digit ring circuit filter, DPLL, FPGA, wideband

Short Content: Abstract: This article introduced briefly realizes the entire digital phase-locked loop (DPLL) principle and the method in FPGA, solves is unstable when the synchronized serial data correspondence's synchronized clock the quick recovery problem; And introduced with emphasis uses in the digital phase-locked loop which the controllable modulus frequency divider realizes the wideband capture's method with to realize the process.Key word: DPLL; FPGA; Digital ring circuit filter; Clock recovery; Wideband Introduction    The digital phase-locked loop (DPLL) technology in the digital communication, the radioelectronics ...